;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Freescale iMX35, ARM1136 ; ; Board : Bluetechnix i.MX35 ; ; Revision : 1.1 ; ; Date : December 15, 2009 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM11 ; platform is ARM11 [PLATFORM_ARM11] JTAG_CHAIN = 5, 4, 5, 4 ; list of IR lenght of all TAP controllers in JTAG chain JTAG_CLOCK = 10, 10000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 10MHz for normal work JTAG_TDO_DELAY = 5 TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = ARM1136, 2 ; TAP is ARM11 CPU CORE0_BREAKMODE = soft ; breakpoint mode CORE0_INIT = INIT_MX35 ; init section for the CPU CORE0_FLASH0 = FLASH_NAND_BOOT ; flash section parameters CORE0_FLASH1 = FLASH_NOR CORE0_ENDIAN = LITTLE ; core is little endian ; workspace in DDR2 ;CORE0_WORKSPACE = 0x80000000, 0x10000 ; workspace for flash programmer ; workspace in internal RAM CORE0_WORKSPACE = 0x10000000, 0x10000 ; workspace for flash programmer CORE0_STARTUP_MODE = RESET ; or RUN ;CORE0_VECTOR_CATCH_MASK = 0xFF CORE0_PATH = "tftp://192.168.3.60" ; default path [INIT_MX35] ; AIPS setup memory write32 0x43f00040 0x00000000 memory write32 0x43f00044 0x00000000 memory write32 0x43f00048 0x00000000 memory write32 0x43f0004C 0x00000000 memory write32 0x43f00050 0x00000000 memory write32 0x43f00000 0x77777777 memory write32 0x43f00004 0x77777777 memory write32 0x53f00040 0x00000000 memory write32 0x53f00044 0x00000000 memory write32 0x53f00048 0x00000000 memory write32 0x53f0004C 0x00000000 memory write32 0x53f00050 0x00000000 memory write32 0x53f00000 0x77777777 memory write32 0x53f00004 0x77777777 ; Clock setup memory write32 0x53F80004 0x00821000 ; first need to set IPU_HND_BYP memory write32 0x53F80004 0x00821000 ; arm clock is 399Mhz and ahb clock is 133Mhz. wait 5 clock normal ; DDR group settings memory write32 0x43fac794 0x0000 ; SDCKE memory write32 0x43fac798 0x0000 ; DQS[3:0] memory write32 0x43fac79c 0x0000 ; SDBA1, SDBA0 memory write32 0x43fac7a0 0x0000 ; SD[31:0] memory write32 0x43fac7a4 0x0000 ; sdclk, DQM ; IO SW PAD Control registers memory write32 0x43FAC368 0x00000002 memory write32 0x43FAC36C 0x00000002 memory write32 0x43FAC370 0x00000002 memory write32 0x43FAC374 0x00000002 memory write32 0x43FAC378 0x00000002 memory write32 0x43FAC37C 0x00000002 memory write32 0x43FAC380 0x00000002 memory write32 0x43FAC384 0x00000002 memory write32 0x43FAC388 0x00000002 memory write32 0x43FAC38C 0x00000002 memory write32 0x43FAC390 0x00000002 memory write32 0x43FAC394 0x00000002 memory write32 0x43FAC398 0x00000002 memory write32 0x43FAC39C 0x00000002 memory write32 0x43FAC3A0 0x00000002 memory write32 0x43FAC3A4 0x00000002 memory write32 0x43FAC3A8 0x00000002 memory write32 0x43FAC3AC 0x00000002 memory write32 0x43FAC3B0 0x00000002 memory write32 0x43FAC3B4 0x00000002 memory write32 0x43FAC3B8 0x00000002 memory write32 0x43FAC3BC 0x00000002 memory write32 0x43FAC3C0 0x00000002 memory write32 0x43FAC3C4 0x00000002 memory write32 0x43FAC3C8 0x00000002 memory write32 0x43FAC3CC 0x00000002 memory write32 0x43FAC3D0 0x00000002 memory write32 0x43FAC3D4 0x00000002 memory write32 0x43FAC3D8 0x00000002 ; DDR data bus SD 0 through 31 memory write32 0x43FAC3DC 0x00000082 memory write32 0x43FAC3E0 0x00000082 memory write32 0x43FAC3E4 0x00000082 memory write32 0x43FAC3E8 0x00000082 memory write32 0x43FAC3EC 0x00000082 memory write32 0x43FAC3F0 0x00000082 memory write32 0x43FAC3F4 0x00000082 memory write32 0x43FAC3F8 0x00000082 memory write32 0x43FAC3FC 0x00000082 memory write32 0x43FAC400 0x00000082 memory write32 0x43FAC404 0x00000082 memory write32 0x43FAC408 0x00000082 memory write32 0x43FAC40C 0x00000082 memory write32 0x43FAC410 0x00000082 memory write32 0x43FAC414 0x00000082 memory write32 0x43FAC418 0x00000082 memory write32 0x43FAC41c 0x00000082 memory write32 0x43FAC420 0x00000082 memory write32 0x43FAC424 0x00000082 memory write32 0x43FAC428 0x00000082 memory write32 0x43FAC42c 0x00000082 memory write32 0x43FAC430 0x00000082 memory write32 0x43FAC434 0x00000082 memory write32 0x43FAC438 0x00000082 memory write32 0x43FAC43c 0x00000082 memory write32 0x43FAC440 0x00000082 memory write32 0x43FAC444 0x00000082 memory write32 0x43FAC448 0x00000082 memory write32 0x43FAC44c 0x00000082 memory write32 0x43FAC450 0x00000082 memory write32 0x43FAC454 0x00000082 memory write32 0x43FAC458 0x00000082 ; DQM setup memory write32 0x43FAC45c 0x00000082 memory write32 0x43FAC460 0x00000082 memory write32 0x43FAC464 0x00000082 memory write32 0x43FAC468 0x00000082 memory write32 0x43FAC46c 0x00000002 memory write32 0x43FAC470 0x00000002 memory write32 0x43FAC474 0x00000002 memory write32 0x43FAC478 0x00000002 memory write32 0x43FAC47c 0x00000002 memory write32 0x43FAC480 0x00000002 ; CSD0 memory write32 0x43FAC484 0x00000002 ; CSD1 memory write32 0x43FAC488 0x00000002 memory write32 0x43FAC48c 0x00000002 memory write32 0x43FAC490 0x00000002 memory write32 0x43FAC494 0x00000002 memory write32 0x43FAC498 0x00000002 memory write32 0x43FAC49c 0x00000002 memory write32 0x43FAC4A0 0x00000002 memory write32 0x43FAC4A4 0x00000002 ; RAS memory write32 0x43FAC4A8 0x00000002 ; CAS memory write32 0x43FAC4Ac 0x00000002 ; SDWE memory write32 0x43FAC4B0 0x00000002 ; SDCKE0 memory write32 0x43FAC4B4 0x00000002 ; SDCKE1 memory write32 0x43FAC4B8 0x00000002 ; SDCLK ; SDQS0 through SDQS3 memory write32 0x43FAC4Bc 0x00000082 memory write32 0x43FAC4C0 0x00000082 memory write32 0x43FAC4C4 0x00000082 memory write32 0x43FAC4C8 0x00000082 ; ESD_MISC : enable DDR2 memory write32 0xB8001010 0x00000304 ; ESD_ESDCFG0 : set timing paramters ;memory write32 0xB8001004 0x007ffC2f memory write32 0xB8001004 0x00255418 ; ESD_ESDCTL0 : select Prechare-All mode memory write32 0xB8001000 0x92120000 ; DDR2 : Prechare-All memory write8 0x80000400 0x12345678 ; ESD_ESDCTL0 : select Load-Mode-Register mode memory write32 0xB8001000 0xB2120000 ; DDR2 : Load reg EMR2 memory write8 0x84000000 0xda ; DDR2 : Load reg EMR3 memory write8 0x86000000 0xda ; DDR2 : Load reg EMR1 -- enable DLL memory write8 0x82000400 0xda ; DDR2 : Load reg MR -- reset DLL memory write8 0x80000333 0xda ; ESD_ESDCTL0 : select Prechare-All mode memory write32 0xB8001000 0x92120000 ; DDR2 : Prechare-All memory write8 0x80000400 0x12345678 ; ESD_ESDCTL0 : select Manual-Refresh mode memory write32 0xB8001000 0xA2120000 ; DDR2 : Manual-Refresh 2 times memory write32 0x80000000 0x87654321 memory write32 0x80000000 0x87654321 ; ESD_ESDCTL0 : select Load-Mode-Register mode memory write32 0xB8001000 0xB2120000 ; DDR2 : Load reg MR -- CL3, BL=8, end DLL reset memory write8 0x80000233 0xda ; DDR2 : Load reg EMR1 -- OCD default memory write8 0x82000780 0xda ; DDR2 : Load reg EMR1 -- OCD exit memory write8 0x82000400 0xda ; ODT disabled ; ESD_ESDCTL0 : select normal-operation mode ; DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit ; disable PWT & PRCT ; disable Auto-Refresh memory write32 0xB8001000 0x82120080 ;# ESD_ESDCTL0 : enable Auto-Refresh memory write32 0xB8001000 0x82126080 memory write32 0xB8001008 0x00002000 ; Adjust the ESDCDLY5 register memory write32 0xB8001020 0x00F48000 ; this is the default value memory write32 0xB8001024 0x00F48000 ; this is the default value memory write32 0xB8001028 0x00F48000 ; this is the default value memory write32 0xB800102c 0x00F48000 ; this is the default value memory write32 0xB8001030 0x00017F00 ; recommended from Vesy ; make force measure with the dedicated bit (Bit 7 at ESDMISC) ;memory write32 0xB8001010 0x00000384 ;wait 10 ;memory write32 0xB8001010 0x00000304 ; dummy write to DDR memory to set DQS low memory write32 0x80000000 0x00000000 [FLASH_NOR] CHIP = CFI_FLASH ; flash chip ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xA0000000 ; chip is mapped at 0x1000000 FILE = "test512k.bin", 0xA0000000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_NAND_BOOT] CHIP = NAND_FLASH CPU = iMX35 ADDR_BASE = 0 FILE = "test512k.bin", 0x0000000 SWAP_BI = NO ; SWAP_BI and BAD_BLOCK_TABLE BAD_BLOCK_TABLE = NO ;YES ; are mutually exclusive ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE ;TCP_PORT = 2001 TCP_PORT = 0 [TELNET] PROMPT = "mx35> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = redboot 3 = prog [erase] ; erase all flash halt flash erase [redboot] ; load RedBoot in DDR2 halt memory load redboot.bin 0x80000000 set pc 0x80000000 go [prog] ; program flash halt flash prog redboot.bin bin 0x0 erase reset run