;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Samsung S3C6410, ARM1176 ; ; Revision : 1.0 ; ; Date : March 21, 2011 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM11 ; platform is ARM11 [PLATFORM_ARM11] JTAG_CHAIN = 5,4 ; list of IR lenght of all TAP controllers in JTAG chain JTAG_CLOCK = 500, 25000 ; JTAG Clock in [kHz] - 500kHz jtag clock for init operations and 25MHz for normal work JTAG_TDO_DELAY = 10 TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 50 CORE0 = ARM1176, 0 ; TAP is ARM7TDMI CPU CORE0_BREAKMODE = soft ; breakpoint mode CORE0_INIT = INIT_S3C6410 ; init section for the CPU CORE0_FLASH0 = FLASH_28F512M29 ; Numonyx (Micron) flash1 CORE0_FLASH1 = FLASH_K8P5516UZB ; Samsung K8P5516UZB-EI4E flash2 CORE0_FLASH2 = I2C_EEPROM CORE0_ENDIAN = LITTLE ; core is little endian ;CORE0_WORKSPACE = 0xc000000, 0x2000 ; internal SRAM CORE0_WORKSPACE = 0x50000000, 0x10000 ; external SDRAM CORE0_STARTUP_MODE = RESET ;CORE0_USE_FAST_DOWNLOAD = YES ;CORE0_VECTOR_CATCH_MASK = 0xFF ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "ftp://jtag:peedi@172.21.10.21" ;CORE0_PATH = "card://" CORE0_FILE = "arm11.bin", 0xA0000000 [INIT_S3C6410] ; System controller setting echo "Clock & Timer setting" set cpsr 0xd3 ;PER.S C15:0x42F 0x70000013 ; Peripheral Port Enable set ppmr 0x70000013 ; Peripheral Port Enable mem wr 0x7e004000 0x0 ; Disable Watchdog ;mem wr 0x7e00f120 0x1000 ; CS0:16bit,Mem1:32bit,CS2=SROMC mem wr 0x7e00f120 0x1080 ; CS0:16bit,Mem1:16bit,CS2=SROMC ;mem wr 0x7e00f120 0x0003 ; CS0:8 bit,Mem1:32bit,CS2=NAND ;mem wr 0x7e00f120 0x1002 ; CS0:16bit,Mem1:32bit,CS2=OND mem wr 0x70000000 0x00000011 ;SROM_BW: Bank0 & Bank1 16-bit echo "Operating Mode Change to Sync Mode" mem wr 0x7e00f900 0x805E ; Change SYNCMUX[6] to "1" wait 10 ; Wait for a while ... mem wr 0x7e00f900 0x80DE ; Assert SYNCREQ&VICSYNCEN to wait 10 ; "1" (rb1004 modify) while ; Others[11:8] to 0xF mem wr 0x7e00f000 0xffff ; APLL Lock Time mem wr 0x7e00f004 0xffff ; MPLL Lock Time mem wr 0x7e00f020 0x1047310 ; ARMCLK:HCLK:PCLK = 1:4:16 mem wr 0x7e00f00c 0x81900302 ; A:400, P:3, S:2 => 400MHz mem wr 0x7e00f010 0x81900303 ; M:400, P:3, S:3 => 200MHz mem wr 0x7e00f01c 0x3 ; APLL/MPLL Clock Select ; DRAM Initialization echo "DRAM Initialization" mem wr 0x7e001004 0x4 ; Enter the Config State mem wr 0x7e001010 0x30C ; Refresh Period register (7800ns),100MHz 0x30E ;mem wr 0x7e001010 0x40E ; Refresh Period register (7800ns),133MHz 0x40E mem wr 0x7e001014 0x6 ; CAS Latency = 3 mem wr 0x7e001018 0x1 ; T_DQSS mem wr 0x7e00101c 0x2 ; T_MRD mem wr 0x7e001020 0x7 ; T_RAS(45ns) mem wr 0x7e001024 0xA ; T_RC(67.5ns) mem wr 0x7e001028 0xC ; T_RCD(22.5ns) = 4, Scheduled RCD = 1 mem wr 0x7e00102C 0x10B ; T_RFC(80ns) = 11, Scheduled RFC= 8 mem wr 0x7e001030 0xC ; T_RP(22.5ns) = 4, Scheduled RP = 1 mem wr 0x7e001034 0x3 ; T_RRD(15ns)=3 mem wr 0x7e001038 0x3 ; T_WR(15ns)=3 mem wr 0x7e00103C 0x2 ; T_WTR mem wr 0x7e001040 0x2 ; T_XP (1tck + tIS(1.5ns)) mem wr 0x7e001044 0x11 ; T_XSR(120ns) mem wr 0x7e001048 0x11 ; T_ESR echo "Memory Configuration Register" mem wr 0x7e00100C 0x80010012 ; 1 CKE, 1Chip, 4burst, Always, AP[10], ; ROW/Column bit echo "Memory Configuration Register 2" ;mem wr 0x7e00104C 0x0B41 ; Read delay 1 Cycle, mDDR, 32bit, Sync. mem wr 0x7e00104C 0x0B01 ; Read delay 1 Cycle, mDDR, 16bit, Sync. echo "Chip 0 Configuration" mem wr 0x7e001200 0x150F8 ; Bank-ROW-Column, 0x5000_0000 ~ 0x57ff_ffff ; (128MB) echo "Memory Direct Command" mem wr 0x7e001008 0xc0000 ; Chip0 Direct Command :NOP5 mem wr 0x7e001008 0x0 ; Chip0 Direct Command :PreCharge all mem wr 0x7e001008 0x40000 ; Chip0 Direct Command :AutoRefresh mem wr 0x7e001008 0x40000 ; Chip0 Direct Command :AutoRefresh mem wr 0x7e001008 0xA0000 ; EMRS, DS:Full, PASR:Full mem wr 0x7e001008 0x80032 ; MRS, CAS3, BL4 mem wr 0x7e001004 0x0 ; Enable DMC1 [FLASH_28F512M29] ; Numonyx (Micron) ;CHIP = 28F512M29 ; flash chip CHIP = CFI_FLASH ; autodetect FLASH ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0x10000000 ; chip is mapped at 0x1000000 FILE = "dump_flash1.bin", 0x10000000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_K8P5516UZB] ; Samsung ;CHIP = K8P5516UZB ; flash chip CHIP = CFI_FLASH ; autodetect FLASH ACCESS_METHOD = AGENT ; program method CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0x18000000 ; chip is mapped at 0x1800000 FILE = "dump_flash2.bin", 0x18000000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [I2C_EEPROM] CHIP = I2C_EEPROM CPU = GENERIC_I2C I2C_ADDR = 0x50 ; The first byte in the I2C communication, ; which carries the chip address in the bus CHIP_SIZE = 8192, 32 ; 8K chip, 32-byte write page SDA_SET = 0x7F008024 OR 0x00000040 ; expression to perform SDA = 1 SDA_CLR = 0x7F008024 AND 0xFFFFFFB0 ; expression to perform SDA = 0 SDA_OUT = 0x7F008020 OR 0x01000000 ; expression to make SDA output SDA_IN = 0x7F008020 AND 0xF0FFFFFF ; expression to make SDA input SCL_SET = 0x7F008024 OR 0x00000020 ; expression to perform SCL = 1 SCL_CLR = 0x7F008024 AND 0xFFFFFFDF ; expression to perform SCL = 0 SDA_READ = 0x7F008024 AND 0x00000040 ; expression to read SDA I2C_DELAY = 1 ; Number of empty loops, used to achieve ; the I2C clock period FILE = "test.bin", 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "s3c6410> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash set 0 ; flash erase flash prog %{ftp}flash1_a.bin 0x10000000 erase flash prog %{ftp}flash1_b.bin 0x11090000 erase flash prog %{ftp}flash1_c.bin 0x12060000 erase flash prog %{ftp}flash1_d.bin 0x12280000 erase flash set 1 ; flash erase flash prog %{ftp}flash2_a.bin 0x18000000 erase flash prog %{ftp}flash2_a.bin 0x18800000 erase flash prog %{ftp}flash2_b.bin 0x19FF0000 erase