;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91M55800A ; Board : Ronetix custom board ; ; ; Revision : 1.4 ; ; Date : August 25, 2006 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM ; platform is ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR length of all TAP controller in JTAG chain JTAG_CLOCK = 10, 20000 ; JTAG Clock in [kHz] - 10kHz for init operations and ; 20MHz for normal work ; MAX JTAG clock 33MHz, 16-20MHz is recommended TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 20 ; time between releasing the reset and starting the jtag communication CORE0 = ARM7TDMI ; TAP is ARM7TDMI CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_EB55800 ; init section for EB55800 board CORE0_FLASH0 = FLASH_TC58FVB160 ; FLASH section parameters CORE0_FLASH1 = NAND_FLASH ; FLASH section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE_ADDR = 0x2000100 ; address of workspace for programmer CORE0_WORKSPACE_LEN = 0x2600 ; length of workspace in bytes 1.5KB ; agent + 8KB data buffer ; (min. 2048(0x800) bytes) CORE0_FILE = "example1_ram.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path [INIT_EB55800] memory write 0xFFFF4020 0x004F0002 ; enable main clock wait 100 ; wait to stabilize memory write 0xFFFF4020 0x004F4002 ; switch to main clock memory write 0xFFFF4020 0x3F006802 ; enable PLL wait 100 ; wait to lock memory write 0xFFFF4020 0x3F008722 ; switch to PLL, pres=4, mul=8 memory write 0xFFE00020 0x00000001 ; cancel reset remapping memory write 0xFFE00000 0x010020A5 ; csr0 - Flash at 0x1000000, 2 Ws memory write 0xFFE00004 0x02003029 ; csr1 - RAM at 0x2000000, 2 Ws memory write 0xFFFFF124 0xFFFFFFFF ; disable all interrupts ; setup for the NAND: PB13 - CS mem write 0xFFFF4010 0x6000 ; enable periph. clock for PIOA and PIOB mem write 0xFFFF0000 0x2000 ; PIOB_PER - enable PIO13 mem write 0xFFFF0010 0x2000 ; PIOB_OER - configure as output mem write 0xFFFF0054 0x2000 ; PIOB_MDDR - disable open drain mem write 0xFFFF0030 0x2000 ; set PB13 mem write 0xFFE00008 0x3002126 ; CSR2 - 8-bis, 2 WS [FLASH_TC58FVB160] ; auto detect TC58FVB160 or LH28F800BJE-PTTL/BJHE-PTTL CHIP = TC58FVB160 ; FLASH chip CHIP = LH28F800BJE-PTTL/BJHE-PTTL ; FLASH chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0x1000000 ; chip is mapped at 0x1000000 FILE = "example1_rom.bin", BIN, 0x1000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [NAND_FLASH] CHIP = NAND_FLASH DATA_BASE = 0x03000000 ; data CMD_BASE = 0x03400000 ; commands (CLE) ADDR_BASE = 0x03200000 ; addreses (ALE) FILE = "test.bin", 0x0 ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0xFFFF0034, 0x2000 ; PB13 <- 0 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0xFFFF0030, 0x2000 ; PB13 <- 1 ; list with bad blocks to be marked as bad ;BAD_BLOCKS = 4, 27, 1002 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "at91m55800> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog