;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91RM9200 ; Board : Kwikbyte KB9200 evaluation board ; ; Revision : 1.4 ; ; Date : July 06, 2006 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 20, 20000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 20MHz for normal work ;JTAG_CLOCK = adaptive ; JTAG Clock Adaptive TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 20 ; time between releasing the reset and starting the jtag communication CORE0 = ARM9TDMI ; TAP 0 is ARM9TDMI CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE0_INIT =INIT_KWIK ; init section for KWIKBYTE AT91RM9200 board CORE0_STARTUP_MODE = RESET ; if RESET than no code is executed after reset ; if STOP then PEEDI lets the target execute code for 300 ms. ; if RUN then the target excutes code until stopped by the telnet "halt" command CORE0_FLASH = FLASH_AM29LV017D CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR= 0x20010000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes CORE0_FILE = "myfile.bin", BIN, 0x20010000 ; default file CORE0_PATH = "tftp://192.168.1.1" ; default path ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; ARM9 only: If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 [INIT_KWIK] set cpsr 0xD3 mem write 0xFFFFFC20 0x0000FF01 ; CKGR_MOR (Main osc. register) mem write 0xFFFFFC28 0x2000BF05 ; CKGR_PLLAR mem write 0xFFFFFC28 0x2059BF05 ; CKGR_PLLAR wait 100 mem write 0xFFFFFC30 0x00000100 ; PMC_MCKR wait 100 mem write 0xFFFFFC30 0x00000202 ; PMC_MCKR (MCLK: 0x102 - (180/2)MHZ, 0x202 - (180/3)MHz) wait 100 mem write 0xFFFFFF70 0x01004187 ; SMC2_CSR[0] mem write 0xFFFFFF60 0x00000002 ; EBI_CSA mem write 0xFFFFFF98 0x32112959 ; SDRC_CR mem write 0xFFFFFF90 0x00000012 ; SDRC_MR mem write16 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFFF90 0x00000014 ; SDRC_MR mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write16 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFFF90 0x00000013 ; SDRC_MR mem write16 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFFF94 0x000001A4 ; SDRC_TR mem write16 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFFF90 0x00000010 ; SDRC_MR mem write16 0x20000000 0 ; SDRAM_BASE mem write 0xFFFFFF00 1 ; REMAP set pc 0x20000000 set control 0x107c ; enable cache [FLASH_AM29LV017D] ; auto detect AM29LV010B or AM29LV017D CHIP=AM29LV010B CHIP=AM29LV017D ACCESS_METHOD=AGENT CHECK_ID=YES CHIP_WIDTH=8 CHIP_COUNT=1 BASE_ADDR=0x10000000 FILE="tftp://192.168.1.1/myfile.bin", BIN, 0x10000000 AUTO_ERASE=NO [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "at91> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog [dump_ram] ; dump part of RAM memory dump 0x02000000 0x01000 ram.bin [dump_flash] ; dump part of FLASH memory dump 0x01000000 0x10000 flash.bin