;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91SAM9G45 ; Board : RONETIX PM9G45 ; ATMEL AT91SAM9G45-EK ; ; Revision : 1.3 ; ; Date : Jan 16, 2012 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 3, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 20MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE0_INIT = INIT_9G45 ; init section CORE0_FLASH0 = BOOTSTRAP CORE0_FLASH1 = U-BOOT CORE0_FLASH2 = KERNEL CORE0_FLASH3 = ROOTFS CORE0_FLASH4 = DATAFLASH CORE0_FLASH5 = FIRSTBOOT CORE0_FLASH6 = EBOOT CORE0_FLASH7 = NK CORE0_FLASH8 = SPI_FLASH CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x300000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "nandflash_pm9g45.elf", ELF ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix PM9G45 board (CPU: AT91SAM9G45) ;------------------------------------------------- [INIT_9G45] mem write 0xFFFFFD44 0x3FFF8FFF ; disable watchdog mem write 0xFFFFFD08 0xA5000301 ; user reset enable, enabled by default mem write 0xFFFFFC20 0x2001 ; CKGR_MOR - enable main osc. 12MHz mem write 0xFFFFFC28 0x20C73F03 ; CKGR_PLLA, DIV 3, MULT 199 (0xC7), PLLA 800 MHz wait 2 mem write 0xFFFFFC30 0x00001300 ; PMC_MCKR - set divider wait 2 mem write 0xFFFFFC30 0x00001302 ; PMC_MCKR - switch to PLLA, MDIV 3, MCK 133MHz wait 2 ; switch JTAG clock to 20MHz (the second argument of JTAG_CLOCK) clock normal ; remove this when INIT used for multicore ; DDDR controller 128MB @ 0x70000000 echo Setting DDRAM @ 0x70000000 mem write 0xFFFFFC00 0x04 ; enable DDR2 clock x2 in PMC mem or 0xFFFFEB28 0x2 ; Configure EBI, EBICSA mem write 0xFFFFE620 0x16 ; HDDRSDRC2_MDR, AT91C_DDRC2_DBW_16_BITS | 16-bit DDR mem write 0xFFFFE608 0x3D ; DDRSDRC_CR mem write 0xFFFFE60C 0x21128226 ; DDRSDRC_T0PR mem write 0xFFFFE610 0x02C8100E ; DDRSDRC_T1PR mem write 0xFFFFE614 0x1072 ; DDRSDRC_T2PR mem write 0xFFFFE600 0x1 ; DDRSDRC_MR, NOP command mem write 0x70000000 0 mem write 0xFFFFE600 0x1 mem write 0x70000000 0 mem write 0xFFFFE600 0x2 ; MR, precharge command mem write 0x70000000 0 mem write 0xFFFFE600 0x5 ; MR, extended LMR cmd mem write 0x74000000 0 mem write 0xFFFFE600 0x5 ; MR, extended LMR cmd mem write 0x76000000 0 mem write 0xFFFFE600 0x5 ; MR, extended LMR cmd mem write 0x72000000 0 wait 2 mem or 0xFFFFE608 0x80 ; CR mem write 0xFFFFE600 0x3 ; MR, LMR cmd mem write 0x70000000 0 mem write 0xFFFFE600 0x2 ; MR, precharge command mem write 0x70000000 0 mem write 0xFFFFE600 0x4 ; MR, refresh cmd mem write 0x70000000 0 mem write 0xFFFFE600 0x4 ; MR, refresh cmd mem write 0x70000000 0 mem and 0xFFFFE608 0xFFFFFF7F ; CR mem write 0xFFFFE600 0x3 ; MR, LMR cmd mem write 0x70000000 0 mem or 0xFFFFE608 0x7000 ; step 15, CR, program OCD field mem write 0xFFFFE600 0x5 ; step 16, MR, extended LMR mem write 0x72000000 0 mem and 0xFFFFE608 0xFFFF8FFF ; step 17, OCD exit mem write 0xFFFFE600 0x5 ; step 18, MR ext LMR cmd mem write 0x72000000 0 mem write 0xFFFFE600 0x0 ; step 19, MR, normal mode mem write 0x70000000 0 ; step 20, write access to any address mem write 0xFFFFE604 0x0000040F ; step 21, RTP, refresh count wait 2 ; Setup CS3 mem write 0xFFFFFC10 0xFFFFFFFF ; enable all peripheral clocks mem write 0xFFFFEB28 0x108 ; EBICSA, CS3 - NAND, no pull-ups ; setup CS3 (NAND Flash) echo Settting CS3 mem write 0xFFFFE830 0x00010001 ; SMC_SETUP3 mem write 0xFFFFE834 0x08060806 ; SMC_PULSE3 mem write 0xFFFFE838 0x00080008 ; CYCLE mem write 0xFFFFE83C 0x00130003 ; SMC_MODE3 ; 8-bit ; NAND FLash: configure PIOs in periph mode mem write 0xFFFFF600 0x4000 mem write 0xFFFFF610 0x4000 ; PIOC->PER <- PC14 mem write 0xFFFFF630 0x4000 ; PIOC->SODR, set PC14 to '1' [BOOTSTRAP] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "nandflash_pm9g45.bin" bin 0x0 ; address and value for asserting the Nand Flash Chip select ; [addr] = value CS_ASSERT = 0xFFFFF634, 0x4000 ; address and value for releasing the Nand Flash Chip select ; [addr] = value CS_RELEASE = 0xFFFFF630, 0x4000 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=1146, 1698 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = FF ; how to deal with the OOB (spare) info ; RAW - program 528/2112 bytes from file ; JFFS2 - program 512/2048 bytes from file and add ECC bytes ; FF - program 512/2048 bytes from file, set spare info to 0xFF [U-BOOT] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "u-boot.bin", BIN, 0x20000 CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO OOB_INFO = FF [KERNEL] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 FILE = "uImage.bin", BIN, 0x200000 AUTO_ERASE = NO [ROOTFS] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 FILE = "rootfs.jffs2", BIN, 0x500000 [DATAFLASH] CHIP = AT45_DATAFLASH ; the DataFlash chip will be autodetected CPU = AT91SAM9263 ; AT91 CPU type: AT91RM9200, AT91SAM9261, AT91SAM9263 or AT91SAM7 SPI_DIV = 8 ; AT91RM9200: Fspi = (MCK/2)/SPI_DIV; AT91SAM9261: Fspi = MCK/SPI_DIV; nSPI = 0 ; which SPI controller: 0 or 1 nCS = 0 ; which chip select: 0 - 3 SPI_SPCK = PIOB, A, 2 ; pin definition for SPCK: PIOB, peripheral A, io2 SPI_MISO = PIOB, A, 0 ; pin definition for MISO: PIOB, peripheral A, io0 SPI_MOSI = PIOB, A, 1 ; pin definition for MOSI: PIOB, peripheral A, io1 SPI_CS = PIOB, A, 3 ; pin definition for CS : PIOB, peripheral A, io3 FILE = "test.bin", BIN, 0 [SPI_FLASH] CHIP = SPI25_FLASH ; the DataFlash chip will be autodetected CPU = AT91SAM9263 ; AT91 CPU type: AT91RM9200, AT91SAM9261, AT91SAM9263 or AT91SAM7 SPI_DIV = 8 ; AT91RM9200: Fspi = (MCK/2)/SPI_DIV; AT91SAM9261: Fspi = MCK/SPI_DIV; nSPI = 0 ; which SPI controller: 0 or 1 nCS = 0 ; which chip select: 0 - 3 SPI_SPCK = PIOB, A, 2 ; pin definition for SPCK: PIOB, peripheral A, io2 SPI_MISO = PIOB, A, 0 ; pin definition for MISO: PIOB, peripheral A, io0 SPI_MOSI = PIOB, A, 1 ; pin definition for MOSI: PIOB, peripheral A, io1 SPI_CS = PIOB, A, 3 ; pin definition for CS : PIOB, peripheral A, io3 FILE = "test.bin", BIN, 0 [FIRSTBOOT] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "FIRSTBOOT.nb0", bin, 0x0 CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 [EBOOT] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "EBOOT.nb0", bin, 0x80000 CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 [NK] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "NK.nb0", bin, 0x200000 CS_ASSERT = 0xFFFFF634, 0x4000 CS_RELEASE = 0xFFFFF630, 0x4000 ERASE_BAD_BLOCKS = NO AUTO_ERASE = NO OOB_INFO = JFFS2 [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "PM9G45> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume ; ; Scripts to be executed using front panel buttons ; If AUTORUN is specified, the given script will be executed every time ; a target is connected to PEEDI ; [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = wince [erase] ; erase flash flash set 0 flash erase ; Program all Linux images ; To use the script type in the console: ; run $prog ; [prog] flash set 2 flash erase ; erase NAND Flash flash set 0 flash prog ; program Bootstrap flash set 1 flash prog ; program U-BOOT flash set 2 flash prog ; program kernel flash set 3 flash prog ; program RootFS ; Program all Windows CE 6.0 images ; To use the script type in the console: ; run $wince ; [wince] flash set 5 flash erase ; erase NAND Flash flash prog ; program FIRSTBOOT flash set 6 flash prog ; program EBOOT flash set 7 flash prog ; program NK