;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Fujitsu JADE1 ARM926EJ-S ; Board : custom board ; ; Revision : 1.0 ; ; Date : Dec 2, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] ; PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 25MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM926E, 0, 0x7926009 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_JADE1 ; init section CORE0_FLASH0 = U-BOOT CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x01000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix PM9263 board (CPU: AT91SAM9263) ;------------------------------------------------- [INIT_JADE1] set cpsr 0x000000D3 set control 0x00050078 ; CP15 Control : disable caches ;--- Initialize External Bus Interface --- ; CS0 configuration ;SRAM/Flash Mode Registor mem write 0xfffc0000=0x00000001 ;RDY=OFF,PAGE=OFF,width=16bit(dummy set) ;SRAM/Flash Timing Registor mem write 0xfffc0020=0x055FF00F ;default(dummy set) ;SRAM/Flash Area Registor mem write 0xfffc0040=0x00000020 ;0x02000000/1MB(dummy set) ; CS2 configuration ;SRAM/Flash Mode Registor mem write 0xfffc0008=0x00000001 ;RDY=OFF,PAGE=OFF,width=16bit ;SRAM/Flash Timing Registor mem write 0xfffc0028=0x10022013 ;WIDLC=2,WWEC=1,WADC=1,WACC=3,RIDLC=3,RADC=1,RACC=3 ;SRAM/Flash Area Registor mem write 0xfffc0048=0x00010050 ;0x05000000/2MB ; CS4 configuration of external FLASH 32 MB ;SRAM/Flash Mode Registor mem write 0xfffc0010=0x00000001 ;RDY=OFF,PAGE=OFF,WIDTH=16bit->MPX_MODE_1[1:0] auto set ;SRAM/Flash Timing Registor (HCLK=83.3/80MHz) mem write 0xfffc0030=0x03061007 ;WIDLC=1,WWEC=4,WADC=1,WACC=7,RIDLC=2,RADC=0,RACC=7 ;SRAM/Flash Area Registor mem write 0xfffc0050=0x000F0000 ; -> 32MB [U-BOOT] CHIP = S29GL512N CHECK_ID = YES ACCESS_METHOD = AGENT CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE="u-boot.bin", BIN, 0x10000000 ;FILE="card:u-boot.bin", BIN, 0x10000000 AUTO_ERASE = YES [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "jade1> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 VOLUME = 25 ; ; Scripts to be executed using front panel buttons ; If AUTORUN is specified, the given script will be executed every time ; a target is connected to PEEDI ; [ACTIONS] ; user defined scripts ;AUTORUN = 1 ; executed on every target connect 1 = prog ; Program ; To use the script type in the console: ; run $prog ; [prog] flash set 0 flash prog ; program U-BOOT