;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file ; ; Santerno ; ; Revision : 1.0 ; ; Date : February 19, 2013 ; ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = ARM7, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased and ; are printed on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4, 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 100, 10000 ; JTAG Clock in [kHz] - 100kHz jtag clock for init operations and 10MHz for normal work ; Valid range: 2 - 33000 TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 100 ; lenght of RESET pulse in ms; 0 means no RESET CORE = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE_INIT = INIT_LPC ; init section CORE_FLASH0 = NAND_MLC ; use MLC Hw ECC CORE_FLASH1 = NAND_SLC ; use SLC Hw ECC CORE_FLASH2 = NAND_JFFS2 ; use JFFS2 Sw ECC CORE_FLASH3 = NAND_YAFFS ; use ECC from file CORE_ENDIAN = little CORE_WORKSPACE = 0x08000000, 0x10000 ; 256 KB IRAM starting @ 0x08000000 CORE_PATH = "tftp://192.168.3.1/tito/santerno" ; default path ;CORE_PATH = "card://" ; default path [INIT_LPC] mem wr 0x4000404C 0x100 ; OSC_CTRL MAIN OSC enabled, default capacitance mem wr 0x40004050 0x140 ; SYSCLK_CTRL SYSCLK = MAIN OSC mem wr 0x40004048 0x2 ; PLL397_CTRL PLL397 disabled (since unused) mem wr 0x40004058 0x00020 ; HCLKPLL_CTRL ARM_CLK = 208 MHz (13 * 16) mem wr 0x40004040 0x1 ; HCLKDIV_CTRL DDRAM_CLK stopped, PERIPH_CLK = ARM_CLK, HCLK = ARM_CLK/2 [SLC, MLC, IRAM] mem wr 0x40004058 0x10010 ; HCLKPLL_CTRL (enable) wait 100 ; wait for PLL to stabilize mem wr 0x40004044 0x6 ; PWR_CTRL switch from DIRECT RUN (everything clock by SYSCLK) to RUN ; GPIO mem wr 0x40028004 0x80000 ; P3_OUTP_SET sets GPO 19 to 1 (unlock FLASH write protection) ;mem wr 0x400040C8 0x05 ; Set as SLC NAND mem wr 0x20020010 6 mem wr 0x20020014 0 mem wr 0x20020020 1 mem wr 0x200B8044 0x0000A25E ; MLC_LOCK = 0xA25E unlock protected registers mem wr 0x200B8030 0x00000000 ; MLC_ICR 8-bit, 512B page NAND mem wr 0x200B8044 0x0000A25E ; MLC_LOCK = 0xA25E unlock protected registers mem wr 0x200B8034 0x04618673 ; MLC_TIME_REG mem wr 0x200b8000 0x000000FF ; MLC_CMD = 0xFF reset controller and NAND device [NAND_MLC] CHIP = NAND_FLASH CPU = LPC3XXX_MLC DATA_BASE = 0x200B0000 ; data CMD_BASE = 0x200B8000 ; commands (CLE) ADDR_BASE = 0x200B8004 ; addreses (ALE) FILE = kickstart.bin, BIN, 0 CS_ASSERT = 0x200B804C, 0 CS_RELEASE = 0x200B804C, 1 OOB_INFO = LPC_ECC [NAND_SLC] CHIP = NAND_FLASH CPU = LPC3XXX_SLC FILE = u-boot.bin, BIN, 0x64000 OOB_INFO = LPC_ECC [NAND_JFFS2] CHIP = NAND_FLASH CPU = LPC3XXX_SLC FILE = uImage, BIN, 0x190000 OOB_INFO = JFFS2 [NAND_YAFFS] CHIP = NAND_FLASH CPU = LPC3XXX_SLC FILE = uImage, BIN, 0x190000 OOB_INFO = YAFFS [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; 2023 [TELNET] PROMPT = "DMrocks> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts 1 = prog_all [prog_all] mem write 0x400040C8 2 ; Select MLC NAND controller flash set 0 flash erase flash prog kickstart.bin 0 flash prog stage1.bin 1*32*512 mem write 0x400040C8 5 ; Select SLC NAND controller flash set 1 flash prog u-boot.bin 25*32*512 flash set 2 flash prog env.bin 90*32*512 flash prog uImage bin 100*32*512 flash prog ubi.img bin 356*32*512 ;flash set 3 ; program UBIFS using dump image ;flash prog ubi.bin 0x590000 [dump_env] mem write 0x400040C8 5 ; Select SLC NAND controller flash set 2 flash dump 90*32*512 32*512 env.bin [dump_ubi] mem write 0x400040C8 5 ; Select SLC NAND controller flash set 3 flash dump 356*32*512 0x3C43800 ubi.bin [How to create ubi.img from rootfs/ - Ref. http://processors.wiki.ti.com/index.php/UBIFS_Support] 1. Create ubinize.cfg: [ubifs] mode=ubi image=ubifs.img vol_id=0 vol_size=54MiB vol_type=dynamic vol_name=rootfs vol_flags=autoresize 2. sudo mkfs.ubifs -r rootfs -o ubifs.img -m 512 -e 15360 -c 3700 3. sudo ubinize -o ubi.img -m 512 -p 16KiB ubinize.cfg