;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Marvell MV78100, MV78200 ; Board : Cogent CSB1725, MV78200 ; ; Revision : 1.0 ; ; Date : March 09, 2017 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM ; platform is ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 16MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL WAKEUP_TIME = 500 ; delay from power-up to reset pulse RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 CORE0 = FEROCEON, 0 ; TAP is a Marvell Feroceon CPU CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_CSB1725_D0 ; init section ;CORE0_INIT = INIT_CSB1725_F1 ; init section CORE0_FLASH0 = SPI_FLASH ; flash section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE = 0x1000000, 0x10000 ; workspace for flash programmer ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 ; Internal registers Base Address is 0xD0000000 (by default) [INIT_CSB1725_D0] echo ++ info: init with internal registers base address 0xD0000000 mem write 0xD0020100 0x00000002 ; CPU Configuration Register ; VecInitLoc = 0xFFFF0000 set control 0x00052078 ; CP15 Control - disable caches mem write 0xD0010470 0x01c00541 ; Device Bus NAND Control Register mem write 0xD00104C8 0x80000012 ; Device Bus Sync Control Register ; BootCS Ready Ignore ; Tclk Divide Value = /2 mem write 0xD0010400 0x003e07cf ; Device Bus Read Parameters Register (DEV_BOOTCSn) mem write 0xD0010404 0x000F0F0F ; Device Bus Write Parameters Register (DEV_BOOTCSn) ; Set-up CS0 ;mem write 0xD0010408 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS0) ;mem write 0xD001040C 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS0) ; Set-up CS1 mem write 0xD0010410 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS1) mem write 0xD0010414 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS1) ; Set-up CS2 mem write 0xD0010418 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS2) mem write 0xD001041C 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS2) ; DDR II Micron part number Micron ; System configuration: MClk 400MHz, Size 1024MB, ECC disable mem write 0xD0001400 0x43008C30 ; DDR SDRAM Configuration Register mem write 0xD0001404 0x38543000 ; Dunit Control Low Register mem write 0xD0001408 0x23135441 ; DDR SDRAM Timing (Low) Register mem write 0xD000140C 0x00000A32 ; DDR SDRAM Timing (High) Register mem write 0xD0001410 0x000000DD ; DDR SDRAM Address Control Register mem write 0xD0001414 0x00000000 ; DDR SDRAM Open Pages Control Register mem write 0xD0001418 0x00000000 ; DDR SDRAM Operation Register mem write 0xD000141C 0x00000652 ; DDR SDRAM Mode Register mem write 0xD0001420 0x00000040 ; DDR SDRAM Extended Mode Register mem write 0xD0001424 0x0000F07F ; Dunit Control High Register mem write 0xD0001504 0x3FFFFFF1 ; CS[0]n Size Register mem write 0xD000150C 0x00000000 ; CS[1]n Size Register mem write 0xD0001514 0x00000000 ; CS[2]n Size Register mem write 0xD000151C 0x00000000 ; CS[3]n Size Register mem write 0xD0001494 0x84210000 ; DDR2 SDRAM ODT Control (Low) Register mem write 0xD0001498 0x00000000 ; DDR2 SDRAM ODT Control (High) Register mem write 0xD000149C 0x0000EB0F ; DDR2 Dunit ODT Control Register mem write 0xD0001480 0x00000001 ; DDR SDRAM Initialization Control Register mem write 0xD0020204 0x00000000 ; Main IRQ Interrupt Mask Register mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0020204 0x00000000 ; " mem write 0xD0010604 0x19 ; SPI Configuration Register ; read base address of internal registers ; mem read 0xD0020080 1 ; Internal registers Base Address is 0xF1000000 (remapped by U-BOOT) [INIT_CSB1725_F1] echo ++ info: init with internal registers base address 0xF1000000 mem write 0xF1020100 0x00000002 ; CPU Configuration Register ; VecInitLoc = 0xFFFF0000 set control 0x00052078 ; CP15 Control - disable caches mem write 0xF1010470 0x01c00541 ; Device Bus NAND Control Register mem write 0xF10104C8 0x80000012 ; Device Bus Sync Control Register ; BootCS Ready Ignore ; Tclk Divide Value = /2 mem write 0xF1010400 0x003e07cf ; Device Bus Read Parameters Register (DEV_BOOTCSn) mem write 0xF1010404 0x000F0F0F ; Device Bus Write Parameters Register (DEV_BOOTCSn) ; Set-up CS0 ;mem write 0xF1010408 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS0) ;mem write 0xF101040C 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS0) ; Set-up CS1 mem write 0xF1010410 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS1) mem write 0xF1010414 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS1) ; Set-up CS2 mem write 0xF1010418 0x003e07cf ; Device Bus Read Parameters Register (DEV_CS2) mem write 0xF101041C 0x000F0F0F ; Device Bus Write Parameters Register (DEV_CS2) ; DDR II Micron part number Micron ; System configuration: MClk 400MHz, Size 1024MB, ECC disable mem write 0xF1001400 0x43008C30 ; DDR SDRAM Configuration Register mem write 0xF1001404 0x38543000 ; Dunit Control Low Register mem write 0xF1001408 0x23135441 ; DDR SDRAM Timing (Low) Register mem write 0xF100140C 0x00000A32 ; DDR SDRAM Timing (High) Register mem write 0xF1001410 0x000000DD ; DDR SDRAM Address Control Register mem write 0xF1001414 0x00000000 ; DDR SDRAM Open Pages Control Register mem write 0xF1001418 0x00000000 ; DDR SDRAM Operation Register mem write 0xF100141C 0x00000652 ; DDR SDRAM Mode Register mem write 0xF1001420 0x00000040 ; DDR SDRAM Extended Mode Register mem write 0xF1001424 0x0000F07F ; Dunit Control High Register mem write 0xF1001504 0x3FFFFFF1 ; CS[0]n Size Register mem write 0xF100150C 0x00000000 ; CS[1]n Size Register mem write 0xF1001514 0x00000000 ; CS[2]n Size Register mem write 0xF100151C 0x00000000 ; CS[3]n Size Register mem write 0xF1001494 0x84210000 ; DDR2 SDRAM ODT Control (Low) Register mem write 0xF1001498 0x00000000 ; DDR2 SDRAM ODT Control (High) Register mem write 0xF100149C 0x0000EB0F ; DDR2 Dunit ODT Control Register mem write 0xF1001480 0x00000001 ; DDR SDRAM Initialization Control Register mem write 0xF1020204 0x00000000 ; Main IRQ Interrupt Mask Register mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1020204 0x00000000 ; " mem write 0xF1010604 0x19 ; SPI Configuration Register ; read base address of internal registers ; mem read 0xF1020080 1 ; tested on Cogent CSB1725, MV78200 [SPI_FLASH] CHIP = SPI25_FLASH CPU = FEROCEON FILE = "test256k.bin", bin, 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "fero> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog 3 = dump_ram [erase] ; erase flash flash erase [prog] ; program flash flash prog [dump_ram] ; dump part ot RAM memory dump 0x00000000 0x01000 tftp:ram.bin