;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Freescale iMX1, M9328MX1 ; Board : Freescale M9328MX1ADS ; ; Revision : 1.0 ; ; Date : April 18, 2007 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 1000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 1MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL WAKEUP_TIME = 3000 ; time between releasing the reset and starting the jtag communication RESET_TIME = 500 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = ARM920T, 0 ; TAP 0 is ARM920T CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_MX1ADS ; init section for the MX1ADS board CORE0_FLASH0 = U-BOOT CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x00300000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x00000000 ;------------------------------------------------- ; Init for Freescale M9328MX1ADS board (CPU: M9328MX1) ; memory map: ; SDRAM - 0x08000000 - 64 MB ; Flash - 0x0C000000 - 16 MB ; SRAM - 0x00300000 - 128 KB ;------------------------------------------------- [INIT_MX1ADS] ; Initialize DragonBall MX1 ADS board when using JTAG ; mem write 0x0021b000 0x2f00ac03 ; Select CLKO mux to output HCLK(BCLK) mem write 0x0021b000 0x2f008403 ; 48MHz System Clock mem write 0x00220000 0x00002000 ; CS0 - boot flash, 32 wait states, 8-bit mem write 0x00220004 0x11110301 mem write 0x00220008 0x00000a00 ; CS1 - SRAM, 10 wait states, 32-bit mem write 0x0022000c 0x11110601 mem write 0x00220020 0x00000a00 ; CS4 - External UART, 10 wait states, 8-bit mem write 0x00220024 0x11110301 ; ;Init SDRAM 16Mx16x2 IAM0 CS2 CL2 ; mem write 0x00221000 0x92120200 ; Set Precharge Command mem write 0x08200000 0x00000000 ; Issue Precharge all Command mem write 0x00221000 0xa2120200 ; Set AutoRefresh Command mem write 0x08000000 0x00000000 ; Issue AutoRefresh Command mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x08000000 0x00000000 mem write 0x00221000 0xb2120200 ; Set Mode Register mem write 0x08111800 0x00000000 ; Issue Mode Register Command, Burst Length = 8 mem write 0x00221000 0x82124200 ; Set to Normal Mode mem write 0x0021b80c 0x000003fb ; initialize global peripheral control register mem read 0x00221004 ; read SDRAM control register mem write 0x00221004 0x81020300 ; set normal mode mem write 0x00221004 0xB1020300 ; set load mode register mem read 0x0C08CC00 ; special read to FLASH mem write 0x00221004 0x91020300 ; set pre-charge mode mem read 0x0C100000 ; special read to FLASH mem write 0x00221004 0x81020300 ; set normal mode mem write 0x00220008 0x00000A00 ; SRAM initialization mem write 0x0022000C 0x11110401 ; SRAM initialization mem write 0x0021B000 0x8F008403 ; set CLKO to CLK48M, FCLK to 150 MHz, BCLK to 48 MHz mem write 0x0021B004 0x04632410 ; Set PD=0, MFD=99, MFI=6, MFN=10 150M mem write 0x0021B000 0x00200000 ; Trigger the restart bit(bit 21) mem write 0x0021B000 0xFFFF7FFF ; Program PRESC bit(bit 15) to 0 to divide-by-1 [U-BOOT] CHIP = AM29PDL127H ACCESS_METHOD = AGENT CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x1000000 ;FILE="tftp:eb9261/u-boot.bin", BIN, 0x0C000000 FILE="card:u-boot.bin", BIN, 0x01000000 AUTO_ERASE=YES [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0; 2023 [TELNET] PROMPT = "mx1> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash set 0 flash prog ; program U-BOOT flash set 1 flash prog ; program kernel flash set 2 flash erase ; erase NAND Flash flash prog ; program rootfs [dump_ram] ; dump part of RAM memory dump 0x20000000 0x0100 card:ram.bin