;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale i.MX23 ; Supported board : Freescale i.MX23 EVK ; ; Revision : 1.0 ; ; Date : June 30, 2011 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 1000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 1MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 10 ; lenght of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 10 ; time between releasing the reset and starting the jtag communication CORE0 = ARM926E ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE0_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_IMX233 ; init section ;CORE0_INIT = INIT_LINUX ; init section CORE0_FLASH0 = IMX23_NAND CORE0_FLASH1 = IMX23_SPI CORE0_ENDIAN = little CORE0_WORKSPACE = 0x8000, 0x8000 ; workspace for flash programming CORE0_PATH = "tftp://192.168.3.1" CORE0_FILE = "test.bin", BIN, 0x20000000 CORE_VECTOR_CATCH_MASK = 0x00 [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' set r0 4 ; let the board boot from NAND ;set r0 9 ; let the board boot from Card go wait 20000 stop break del all beep 100 100 ;------------------------------------------------- ; Init for Freescale IMX233 board ; In Linux the sys base address 0xFFFFE000 is mapped to 0xFEFFE000 ;------------------------------------------------- [INIT_IMX233] mem write 0x80040070 0x00000001 ; HW_CLKCTRL_SSP mem write 0x80010000 0x00000000 ; HW_SSP_CTRL0 mem write 0x80010060 0x00000070 ; HW_SSP_CTRL1 mem write 0x80010050 0x00FF0200 ; HW_SSP_TIMING mem write 0x80018148 0x00003FFF clock normal ;Clock control mem write 0x80040080 0x00000000 ; Enable clock to GPMI mem write 0x80040080 0x00000001 ; and set the devider to 1 when the clock is enabled. ;PIN control mem write 0x80018004 0x80000000 ; Set Reset mem write 0x80018008 0x40000000 ; Clear CLK Gate wait 100 mem write 0x80018008 0x80000000 ; Clear Reset mem write 0x80018234 0x00000011 ; RDn and WEn set to 8mA Driver Strenght mem write 0x80018108 0x0000FFFF ; MuxSelect GPMI DATA0..7 mem write 0x80018118 0x000F00CF ; MuxSelect RDn, WRn, R/B0, ALE, CLE mem write 0x80018158 0x03000000 ; MuxSelect CE0n ; mem write 0x80018114 0x0000C000 ; MuxSelect WPn to PIO mem write 0x80018704 0x00800000 ; WPn PIO output enable mem write 0x80018504 0x00800000 ; WPn PIO output "1" ;APBH DMI control mem write 0x80004004 0x80000000 ; Set SFTRST mem write 0x80004008 0x40000000 ; Enable ABPH DMA -> clear CLK GATE wait 100 mem write 0x80004008 0x80000000 ; Enable ABPH DMA -> clear SFTRST mem write 0x80004008 0x30000000 ; Clear burst lenghts mem write 0x80004008 0x0000FF00 ; Clear clock gate mem write 0x80004004 0x00FF0000 ; Reset channels wait 100 mem write 0x80004008 0x000000FF ; Clear Frozen ;GPMI control mem write 0x8000C004 0x80000000 ; Set SRST in GPMI control reg0 mem write 0x8000C008 0x40000000 ; Clear CLKGATE in GPMI control reg0 wait 100 mem write 0x8000C008 0x80000000 ; Clear SRST in GPMI control reg0 ; in control reg1 mem write 0x8000C068 0x00000001 ; Clear GPMI_MODE, so set it to NAND mem write 0x8000C064 0x00000004 ; Set IRQ RdyBsy polarity to R/Bn mem write 0x8000C064 0x00000008 ; Disable write protection mem write 0x8000C064 0x00040000 ; Set BCH ECC mode ;mem write 0x8000C068 0x00040000 ; Set ECC 8 mode ;A BCH controller. ; if the COMPLETE_IRQ bit is set then the BCH if halted/off/not working ; And to clear that bit, first the COMPLETE_IRQ enable bit must to be set mem write 0x8000A004 0x00000101 mem write 0x8000A008 0x00000101 ;ECC BCH controller ; DO THIS ONLY !ONCE! AFTER HARD RESET ; on second soft reset BCH stops working!!! ; !!! mem write 0x8000A004 0x80000000 ; Set SFTRST !!! mem write 0x8000A008 0x40000000 ; Enable Clock wait 100 mem write 0x8000A008 0x80000000 ; Clear SFTRST mem write 0x8000A020 0x00000008 ; For MLC NAND devices, bit errors may occur ; on reads (even on blank block), so this threshold can ; be used to tune the erased block checking algorithm. ; if the COMPLETE_IRQ bit is set then the BCH if halted/off/not working ; And to clear that bit, first the COMPLETE_IRQ enable bit must to be set mem write 0x8000A004 0x00000101 mem write 0x8000A008 0x00000101 [IMX23_SPI] CHIP = SPI25_FLASH ; the SPI FLASH chip will be autodetected CPU = IMX23 ; Blackfin CPU SPI_DIV = 0 FILE = "test.bin", BIN, 0 [IMX23_NAND] CHIP = NAND_FLASH CPU = IMX23 ADDR_BASE = 0 ; Chip Enable FILE = "dimov/test.bin", BIN, 0x000000 ;BAD_BLOCKS = 133, 484, 492, 2259, 3491, 3839, 7465 ERASE_BAD_BLOCKS = YES OOB_INFO = IMX23_BCH NCB_DATA = 0x504D5453,\ ; uint32_t m_u32Fingerprint1; 33 0x06193C50,\ ; uint8_t m_u8DSAMPLE_TIME | uint8_t m_u8AddressSetup| uint8_t m_u8DataHold| uint8_t m_u8DataSetup; 0x00001000,\ ; uint32_t m_u32DataPageSize; //!< 2048 for 2K pages, 4096 for 4K pages. 0x000010DA,\ ; uint32_t m_u32TotalPageSize; //!< 2112 for 2K pages, 4314 for 4K pages. 0x00001000,\ ; uint32_t m_u32SectorsPerBlock; //!< Number of 2K sections per block. 0x00000001,\ ; uint32_t m_u32SectorInPageMask; //!< Mask for handling pages > 2K. 0x00000001,\ ; uint32_t m_u32SectorToPageShift; //!< Address shift for handling pages > 2K. 0x00000001,\ ; uint32_t m_u32NumberOfNANDs; //!< Total Number of NANDs - not used by ROM. 0x00000000,\ ; dummy 0x00000000,\ ; dummy 0x00000000,\ ; dummy 0x2042434E,\ ; uint32_t m_u32Fingerprint2; // @ word offset 10 0x00000003,\ ; uint32_t m_u32NumRowBytes; //!< Number of row bytes in read/write transactions. 0x00000002,\ ; uint32_t m_u32NumColumnBytes; //!< Number of column bytes in read/write transactions. 0x00000001,\ ; uint32_t m_u32TotalInternalDie; //!< Number of separate chips in this NAND. 0x00000001,\ ; uint32_t m_u32InternalPlanesPerDie;//!