;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file ; ; Supported devices : TI OMAP5948 (ARM926E + DSP) ; Board : Custom board ; ; Revision : 1.0 ; ; Date : 13.01.2015 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb_remote or adp REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 8, 4, 38 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 100, 10000 ; JTAG Clock in [kHz] - 100kHz jtag clock for init ; operations and 10MHz for normal work ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL JTAG_TDO_DELAY = AUTO ; set the optimum TDO delay WAKEUP_TIME = 100 ; time between releasing the reset and starting ; the jtag communication RESET_TIME = 0 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = DAVINCI, 1 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: CORE0_BREAKMODE = hard ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_OMAP5948 ; init section CORE0_FLASH0 = U-BOOT CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x10000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes (64Kb) CORE0_PATH = "tftp://192.168.3.1" ; default path ;CORE0_PATH = "card://" ; default path CORE0_FILE = "test.bin", BIN, 0x10000000 ;------------------------------------------------- ; Init for OMAP5948 ;------------------------------------------------- [INIT_OMAP5948] ; reset ARM set cpsr 0x000000D3 ; set supervisor mode set pc 0x00000000 set control 0x00050078 ; CP15 Control : disable caches ; disable ARM9 Watchdog Timer mem write 0xFFFEC808 0x00F5 ; convert WD timer into GP timer mem write 0xFFFEC808 0x00A0 ; mem write 0xFFFEB048 0xAAAA ; stop the wahtchdog timer mem write 0xFFFEB048 0x5555 ; setup DPLL for 96MHz freq mem or16 0xFFFECE08 0x4 ; enable ARM peripheral clock mem w16 0xFFFECE14 0x1 ; release OMAP CLKM reset mem w16 0xFFFECF00 0x2090 ; DPLL lock at 12MHz wait 150 ; wait until frequency is locked mem w16 0xFFFECE18 0x0 ; clocking mode : fully synchronous mem w16 0xFFFECE00 0x100A ; set the clock divisor for frequency 96MHz mem w16 0xFFFECF00 0x2413 ; set the DPLL for new frequency mem w16 0xFFFECE04 0x0 ; ; Setup TIPB (peripheral bus) mem w32 0xFFFEC900 0x0003FF2C ; set access width mem w16 0xFFFECA00 0xFF22 ; ARM private bus mem w16 0xFFFED300 0xFF22 ; ARM public bus ; configure EMIFS (slow external memory: flash) mem w32 0xFFFECC10 0x0000FFF3 ; EMIFS CS0 configuration mem w32 0xFFFECC14 0x0000AAA0 ; EMIFS CS1 configuration mem w32 0xFFFECC18 0x0000FFF3 ; EMIFS CS3 configuration mem w32 0xFFFECC1C 0x00003361 ; EMIFS CS3 configuration mem r32 0xFFFECC0C ; read EMIFS_CONFIG mem w8 0x00000000 0xFF ; reset flash to Read Array mode ; configure EMIFF (fast external memory: SDRAM-Mobile DDR) mem w32 0xFFFECC80 0x00000007 ; SDRAM type : mobile DDR SDRAM in HPHB mode mem w32 0xFFFECC20 0x0014E6FE ; SDRAM config mem w32 0xFFFECC84 0x00000000 ; DDR init : NOP mem w32 0xFFFECC84 0x00000001 ; DDR init : PRECHARGE mem w32 0xFFFECC84 0x00000002 ; DDR init : AUTOREFRESH mem w32 0xFFFECC84 0x00000002 ; DDR init : AUTOREFRESH mem w32 0xFFFECC70 0x00000033 ; DDR init : cas idle 3, page burst 8 mem w32 0xFFFECC78 0x00000000 ; DDR init : self refresh all banks mem w32 0xFFFECCC0 0x00000006 ; DDR init : DDR DDL registers URD mem w32 0xFFFECCCC 0x00000006 ; DDR init : DDR DDL registers LRD mem w32 0xFFFECC64 0x00000006 ; DDR init : DDR DDL registers WRD [U-BOOT] CHIP = CFI_FLASH ; flash chip ACCESS_METHOD = AUTO ; program method auto BASE_ADDR = 0 ; chip is mapped at 0x0000000 FILE = "u-boot.bin", BIN, 0 ; file to program AUTO_ERASE = YES ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 [TELNET] PROMPT = "OMAP5948> " ; telnet prompt [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash set 0 flash prog ; program U-BOOT