;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : Atmel AT91SAM9G35, SAM9G25, SAM9G15, SAM9X25, SAM9X35 ; Board : RONETIX SAM9-CM v2.0 ; ATMEL AT91SAM9x5-EK ; ; Revision : 1.2 ; ; Date : Jan 04, 2015 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may points to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 4 ; list of IR lenghts of all TAP controller in JTAG chain JTAG_CLOCK = 5, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 25MHz for normal work JTAG_TDO_DELAY = 5 ; Valid range: 5 - 33000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 CORE0 = ARM926E, 0 ; TAP 0 is ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern CORE0_INIT = INIT_SAM9 ; init section CORE0_FLASH0 = PMECC_BOOTSTRAP CORE0_FLASH1 = PMECC_U-BOOT CORE0_FLASH2 = PMECC_LINUX CORE0_FLASH3 = PMECC_ROOTFS CORE0_ENDIAN = little CORE0_WORKSPACE_ADDR = 0x20000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "nandflash_sam9-cm.elf", ELF ;------------------------------------------------------------------- ; CORE_VECTOR_CATCH_MASK ; ---------------------- ; If one of the bits is set HIGH and the corresponding exception occurs, the ; processor enters debug state as if a breakpoint has been set on an instruction fetch ; from the relevant exception vector. ; ; bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ;---------------------------------------------------------- ;| fiq | irq | res |d_abort| p_abort| swi | undef | reset | ;---------------------------------------------------------- CORE_VECTOR_CATCH_MASK = 0x00 ;------------------------------------------------- ; Init for Ronetix SAM9-CM board ;------------------------------------------------- [INIT_SAM9] mem write 0xFFFFFE08 0xA5000001 ; Allow user reset mem write 0xFFFFFE44 0x3FFFAFFF ; Disable watchdog ; Initialize main oscillator ; PMC->CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCSEL | CKGR_MOR_MOSCXTEN; mem write 0xFFFFFC20 0x01370001 wait 2 ; Switch to main oscillator ; PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; mem write 0xFFFFFC30 0x00000001 wait 2 ; Initialize PLLA @ 800MHz ; PMC->CKGR_PLLAR = CKGR_PLLAR_STUCKTO1 | CKGR_PLLAR_MULA(199) | ; CKGR_PLLAR_OUTA(0) | CKGR_PLLAR_PLLACOUNT(0x3F) | ; CKGR_PLLAR_DIVA(3); mem write 0xFFFFFC28 0x20C73F03 wait 2 ; Switch to fast clock ; Switch to main oscillator + prescaler ; PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK | PMC_MCKR_MDIV_PCK_DIV3 | PMC_MCKR_PLLADIV2_DIV2; mem write 0xFFFFFC30 0x00001301 ; Switch to PLL + prescaler ; PMC->PMC_MCKR = PMC_MCKR_CSS_PLLA_CLK | PMC_MCKR_MDIV_PCK_DIV3 | PMC_MCKR_PLLADIV2_DIV2; mem write 0xFFFFFC30 0x00001302 clock normal ; EBI chip select assignment mem write 0xFFFFDF20 0x0302000A ; Enable DDR2 clock x2 in PMC ; PMC->PMC_SCER = PMC_SCER_DDRCK ; mem write 0xFFFFFC00 0x04 ; Configure the DDR controller ; -----------------------Step 1------------------- ; Program the memory device type ; ------------------------------------------------ ; REG_DDRSDRC_MD = (DDRSDRC_MD_DBW | DDRSDRC_MD_MD(6)); mem write 0xFFFFE820 0x16 ; -----------------------Step 2------------------- ; 1. Program the features of DDR2-SDRAM device into ; the Configuration Register. ; 2. Program the features of DDR2-SDRAM device into ; the Timing Register HDDRSDRC2_T0PR. ; 3. Program the features of DDR2-SDRAM device into ; the Timing Register HDDRSDRC2_T1PR. ; 4. Program the features of DDR2-SDRAM device into ; the Timing Register HDDRSDRC2_T2PR. ; ------------------------------------------------ ; REG_DDRSDRC_CR = (DDRSDRC_CR_NC(1) | // 10 column bits (1K) ; DDRSDRC_CR_NR(2) | // 13 row bits (8K) ; DDRSDRC_CR_CAS(3)| // CAS Latency 3 ; DDRSDRC_CR_DS | // Output Driver Impedance Control ; (0x1 << 20) // DDRSDRC_CR_8Bank ; ); // DLL not reset mem write 0xFFFFE808 0x100139 ; assume timings for 7.5ns min clock period ; REG_DDRSDRC_T0PR = (DDRSDRC_T0PR_TRAS(6) | // 6 * 7.5 = 45 ns ; DDRSDRC_T0PR_TRCD(2) | // 2 * 7.5 = 15 ns ; DDRSDRC_T0PR_TWR(2) | // 2 * 7.5 = 15 ns ; DDRSDRC_T0PR_TRC(8) | // 8 * 7.5 = 60 ns ; DDRSDRC_T0PR_TRP(2) | // 2 * 7.5 = 15 ns ; DDRSDRC_T0PR_TRRD(1) | // 2 * 7.5 = 15 ns ; DDRSDRC_T0PR_TWTR(1) | // 2 clock cycle ; DDRSDRC_T0PR_TMRD(2)); // 2 clock cycles mem write 0xFFFFE80C 0x21128226 ; REG_DDRSDRC_T1PR = (DDRSDRC_T1PR_TXP(2) | // 2 * 7.5 = 15 ns ; DDRSDRC_T1PR_TXSRD(208) | // 200 clock cycles, TXSRD: Exit self refresh delay to Read command ; DDRSDRC_T1PR_TXSNR(20) | // 16 * 7.5 = 120 ns TXSNR: Exit self refresh delay to non read command ; DDRSDRC_T1PR_TRFC(18)); mem write 0xFFFFE810 0x02D01412 ; REG_DDRSDRC_T2PR = (DDRSDRC_T2PR_TRTP(2) | ; 2 * 7.5 = 15 ns ; DDRSDRC_T2PR_TRPA(3) | ; DDRSDRC_T2PR_TXARDS(7) | // 7 clock cycles ; DDRSDRC_T2PR_TXARD(7)); // 2 clock cycles mem write 0xFFFFE814 0x2377 ; -----------------------Step 3------------------- ; An NOP command is issued to the DDR2-SDRAM to ; enable clock. ; ------------------------------------------------ mem write 0xFFFFE800 0x1 mem write 0x20000000 0x0 ; A minimum pause of 200uS s is provided to precede any signal toggle. wait 1 ; Now clocks which drive DDR2-SDRAM device are enabled ; -----------------------Step 4------------------- ; An NOP command is issued to the DDR2-SDRAM ; ------------------------------------------------ mem write 0xFFFFE800 0x1 mem write 0x20000000 0x0 ; Now CKE is driven high. ; -----------------------Step 5------------------- ; An all banks precharge command is issued to the ; DDR2-SDRAM. ; ------------------------------------------------ ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(2); mem write 0xFFFFE800 0x2 mem write 0x20000000 0x0 ; -----------------------Step 6------------------- ; An Extended Mode Register set (EMRS2) cycle is ; issued to chose between commercialor high ; temperature operations ; ------------------------------------------------ ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(5); mem write 0xFFFFE800 0x5 mem write 0x22000000 0x0 ; The write address must be chosen so that BA[1] is set to 1 and BA[0] are set to 0. ; -----------------------Step 7------------------- ; An Extended Mode Register set (EMRS3) cycle is ; issued to set all registers to 0. ; ------------------------------------------------ ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(5); mem write 0xFFFFE800 0x5 mem write 0x23000000 0x0 ; The write address must be chosen so that BA[1] is set to 1 and BA[0] are set to 1. ; -----------------------Step 8------------------- ; An Extended Mode Register set (EMRS1) cycle is ; issued to enable DLL. ; ------------------------------------------------ ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(5); mem write 0xFFFFE800 0x5 mem write 0x21000000 0x0 ; The write address must be chosen so that BA[1] and BA[0] are set to 0. ; -----------------------Step 9------------------- ; Program DLL field into the Configuration Register. ; ------------------------------------------------- ; cr = REG_DDRSDRC_CR; ; REG_DDRSDRC_CR = (cr | DDRSDRC_CR_DLL | DDRSDRC_CR_DIC); mem or 0xFFFFE808 0x180 ; -----------------------Step 10------------------- ; A Mode Register set (MRS) cycle is issued to reset ; DLL. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(3); mem write 0xFFFFE800 0x3 mem write 0x20000000 0x0 ; The write address must be chosen so that BA[1:0] bits are set to 0. ; -----------------------Step 11------------------- ; An all banks precharge command is issued to the ; DDR2-SDRAM. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(2); mem write 0xFFFFE800 0x2 mem write 0x20000000 0x0 ; Perform a write access to any DDR2-SDRAM address to acknowledge this command. ; -----------------------Step 12------------------- ; Two auto-refresh (CBR) cycles are provided. ; Program the auto refresh command (CBR) into the ; Mode Register. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(4); mem write 0xFFFFE800 0x4 mem write 0x20000000 0x0 ; Performs a write access to any DDR2-SDRAM location twice to acknowledge these commands. ; Set 2nd CBR ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(4); mem write 0xFFFFE800 0x4 mem write 0x20000000 0x0 ; Performs a write access to any DDR2-SDRAM location twice to acknowledge these commands. ; -----------------------Step 13------------------- ; Program DLL field into the Configuration Register ; to low(Disable DLL reset). ; ------------------------------------------------- ; cr = REG_DDRSDRC_CR; ; REG_DDRSDRC_CR = (cr & ((unsigned int)(~DDRSDRC_CR_DLL))); mem and 0xFFFFE808 0xFFFFFF7F ; -----------------------Step 14------------------- ; A Mode Register set (MRS) cycle is issued to ; program the parameters of the DDR2-SDRAM devices ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(3); mem write 0xFFFFE800 0x3 mem write 0x20000000 0x0 ; The write address must be chosen so that BA[1:0] are set to 0. ; -----------------------Step 15------------------- ; Program OCD field into the Configuration Register ; to high (OCD calibration default) ; ------------------------------------------------- ; cr = REG_DDRSDRC_CR; ; REG_DDRSDRC_CR = (cr | DDRSDRC_CR_OCD(7)); mem or 0xFFFFE808 0x7000 ; -----------------------Step 16------------------- ; An Extended Mode Register set (EMRS1) cycle is ; issued to OCD default value. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(5); mem write 0xFFFFE800 0x5 mem write 0x21000000 0x0 ; The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1. ; -----------------------Step 17------------------- ; Program OCD field into the Configuration Register ; to low (OCD calibration mode exit). ; ------------------------------------------------- ; cr = REG_DDRSDRC_CR; ; REG_DDRSDRC_CR = (cr & ((unsigned int)(~DDRSDRC_CR_OCD_Msk))); mem and 0xFFFFE808 0xFFFF8FFF ; -----------------------Step 18------------------- ; An Extended Mode Register set (EMRS1) cycle is ; issued to enable OCD exit. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(5); mem write 0xFFFFE800 0x5 mem write 0x21000000 0x0 ; The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1. ; -----------------------Step 19,20------------------- ; A mode Normal command is provided. Program the ; Normal mode into Mode Register. ; ------------------------------------------------- ; REG_DDRSDRC_MR = DDRSDRC_MR_MODE(0); mem write 0xFFFFE800 0x0 mem write 0x20000000 0x0 ; Perform a write access to any DDR2-SDRAM address. ; -----------------------Step 21------------------- ; Write the refresh rate into the count field in the ; Refresh Timer register. The DDR2-SDRAM device requires a ; refresh every 15.625uS or 7.81uS. With a 100 ; MHz frequency, the refresh timer count register must to ; be set with (15.625 /100 MHz) = 1562 i.e. 0x061A or ; (7.81 /100MHz) = 781 i.e. 0x030d ; ------------------------------------------------- ; REG_DDRSDRC_RTR = 0x497; mem write 0xFFFFE804 0x00000497 ; wait for end of calibration wait 2 ;--------------------------------------------------- ; configure NAND Flash ;--------------------------------------------------- mem write 0xFFFFFC10 0xFFFFFFFF ; enable all peripheral clocks mem write 0xFFFFEA30 0x01020102 ; SMC_SETUP3 mem write 0xFFFFEA34 0x05030503 ; SMC_PULSE3 mem write 0xFFFFEA38 0x00080008 ; CYCLE mem write 0xFFFFEA3C 0x00030003 ; SMC_MODE3 ; 8-bit ; NAND FLash: configure PIOs in periph mode mem write 0xFFFFFA04 0x3FCF ; define PD[0..13] as their NAND signals mem write 0xFFFFFA00 0x0030 ; but define PD4 (NAND_CS), PD5 (NAND_RD/BY) as PIO mem write 0xFFFFFA14 0x0020 ; PIOC->ODR <- PD5 is an input mem write 0xFFFFFA10 0x0010 ; PIOC->OER <- PD4 is an output mem write 0xFFFFFA30 0x0010 ; PIOC->SODR, set PD4 to '1' [PMECC_BOOTSTRAP] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "at91sam9x5ek-nandflashboot-3.1.bin", BIN, 0x0 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC CPU = AT91SAM9x5 NUM_ECC = 2 HEADER = YES [PMECC_U-BOOT] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "u-boot.bin", BIN, 0x40000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC CPU = AT91SAM9x5 NUM_ECC = 2 HEADER = NO [PMECC_LINUX] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "uImage.bin", BIN, 0x200000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC CPU = AT91SAM9x5 NUM_ECC = 2 HEADER = NO [PMECC_ROOTFS] CHIP = NAND_FLASH DATA_BASE = 0x40000000 ; data CMD_BASE = 0x40400000 ; addreses (CLE) ADDR_BASE = 0x40200000 ; commands (ALE) FILE = "rootfs.ubi", BIN, 0x800000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC CPU = AT91SAM9x5 NUM_ECC = 2 HEADER = NO [SERIAL] BAUD=115200 STOP_BITS=1 PARITY=NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "SAM9-CM> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] VOLUME = 25 ; beeper volume ; ; Scripts to be executed using front panel buttons ; If AUTORUN is specified, the given script will be executed every time ; a target is connected to PEEDI ; [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash 5 = wince [erase] ; erase flash flash erase ; Program all Linux images ; To use the script type in the console: ; run $prog ; [prog] flash set 2 flash erase ; erase NAND Flash flash set 0 flash prog ; program Bootstrap flash set 1 flash prog ; program U-BOOT flash set 2 flash prog ; program kernel flash set 3 flash prog ; program RootFS [test] mem test 0x20000000 0x100000 flash info f p test16k.bin f v f e