;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : TI DaVinci TMS320DM355 (ARM926E + DSP) ; Board : DM365 EVM ; NAND Flash : MT29F16G08QAA, 2KB page, 128 pages/block, 256KB block ; ; Revision : 1.1 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = none ; no license no more REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 6, 4, 5 ; For prototype board, with penta ;JTAG_CHAIN = 6, 4 ; For prototype board, with penta TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL ;WAKEUP_TIME = 300 ; time between releasing the reset and starting the jtag communication RESET_TIME = 100 ; lenght of RESET pulse in ms; 0 means no RESET RESET_TYPE = ICEPICK-C, 0, 1 CORE0 = ARM926E, 1 ; TAP 1 is DaVinci ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern JTAG_CLOCK = 500, 20000 ; JTAG Clock in [kHz] - 5kHz for init CORE0_INIT = INIT_DAVINCI ; init section for DaVinci CPU CORE0_FLASH0 = NAND_UBL CORE0_FLASH1 = NAND_UBOOT CORE0_FLASH2 = NAND_UBOOT_ENV CORE0_FLASH3 = NAND_KERNEL CORE0_FLASH4 = NAND_RAMDISK CORE0_FLASH5 = NAND_NAND2 CORE0_ENDIAN = little CORE0_VECTOR_CATCH_MASK = 0xFF ; worksapce in SRAM ;CORE0_WORKSPACE 0x10000, 0x8000 ; workspace in DDR2 CORE0_WORKSPACE 0x80000000, 0x10000 CORE0_PATH = "tftp://192.168.3.1/dm365/" ;------------------------------------- ; init for TMS320DM355 ;------------------------------------- [INIT_DAVINCI] m w 0x01C40048 0x243F0FF8 ; Peripheral Clock control set CPSR 0x400000D3 ; Set to supervisor mode, disable IRQ/FIQ echo Disable ARM interrupts mem wr 0x01c48020 4 mem wr 0x01c48024 0 mem wr 0x01c48018 0 mem wr 0x01c4801c 0 mem wr 0x01c48000 0xffffffff mem wr 0x01c48004 0xffffffff mem wr 0x01c48008 0xffffffff mem wr 0x01c4800c 0xffffffff wait 200 echo Power On NAND; mem and 4*14+0x01C41A00 0xFFFFFFE0 ; Step 2 - Set MDCTLx.NEXT to new state mem or 4*14+0x01C41A00 3 mem or 0x01C41120 1 ; Step 3 - Start power transition ( set PTCMD.GO to 1 ) wait 100 ; Step 4 - Wait for PTSTAT.GOSTAT to clear echo Setup Pin Mux mem wr 0x01C40000 0x00FD0000 ; Video Yin, SD0, McBSP, SD1_CLK mem wr 0x01C40004 0x00145555 ; Video Cout, EXTCLK, FIELD mem wr 0x01C40008 0x00000055 ; EMIFA mem wr 0x01C4000C 0x375AFFFF ; SPI0, I2C, UART0, ENET, MDIO mem wr 0x01C40010 0x55556555 ; SD1, SPI1, SPI2, SPI4, USBDRVVBUS echo Setup PLL1 ; CLKIN = 24MHz, PLL = 486MHz mem and 0x01c40900 0xFFFFFFFD ; Power up PLL mem or 0x01c40900 0x00000010 ; Put PLL in disable mode mem and 0x01c40900 0xFFFFFFEF ; Take PLL out of disable mode mem and 0x01c40900 0xFFFFFEFF ; Onchip Oscillator mem and 0x01c40900 0xFFFFFFDF ; Clear PLLENSRC mem and 0x01c40900 0xFFFFFFFE ; Set PLL in bypass wait 150 mem or 0x01c40900 0x0008 ; Put PLL in reset mem and 0x01c40900 0xFFFFFFF7 ; Take PLL out of reset mem and 0x01c40900 0xFFFFFFEF ; Enable PLL wait 150 ; Wait for PLL to stabilize ; PLLOUT = (OSCIN / prediv) * 2 * (pllm / postdiv) = (24/8) * 2 * (81/1) = 486MHz mem wr 0x01c40910 81 mem wr 0x01c40914 0x8007 wait 100 mem wr 0x01c40908 0x00470000 ; Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 mem wr 0x01c40908 0x00460000 ; Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 mem wr 0x01c40908 0x00400000 ; Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 mem wr 0x01c40908 0x00410000 ; Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 mem wr 0x01c40928 0x8000 mem wr 0x01c40920 0x8001 ; 486/2 = 243Mhz -> MJCP/HDVICP(Bus) mem wr 0x01c40960 0x8003 ; 486/4 = 121.5Mhz-> EDMA/Peripheral CFG0 mem wr 0x01c40964 0x8001 ; 486/2 = 243Mhz -> VPSS mem wr 0x01c40968 0x8011 ; 486/18 = 27Mhz -> VENC alternate for SD mem wr 0x01c4096c 0x8000 ; 486/2 = 243Mhz -> DDR (DDR has internal /2 divider) mem wr 0x01c40970 0x8004 ; 486/5 = 97.2MHz -> MMC0/SD0 mem wr 0x01c40974 0x8001 ; 486/2 = 243MHz -> CLKOUT mem or 0x01c40938 0x0001 ; Set GOSET wait 500 ; Wait for PLL to lock mem wr 0x01c40900 0x0001 ; Enable PLL echo Setup PLL2 ; CLKIN = 24MHz, PLL = 594MHz mem and 0x01c40d00 0xFFFFFFFD ; Power up PLL mem or 0x01c40d00 0x00000010 ; Put PLL in disable mode mem and 0x01c40d00 0xFFFFFFEF ; Take PLL out of disable mode mem and 0x01c40d00 0xFFFFFEFF ; Onchip Oscillator mem and 0x01c40d00 0xFFFFFFDF ; Clear PLLENSRC mem and 0x01c40d00 0xFFFFFFFE ; Set PLL in bypass wait 150 mem or 0x01c40d00 0x0008 ; Put PLL in reset mem and 0x01c40d00 0xFFFFFFF7 ; Take PLL out of reset mem and 0x01c40d00 0xFFFFFFEF ; Enable PLL wait 150 ; Wait for PLL to stabilize mem wr 0x01c40d10 99 ; PLL out = (24/8) * 99 * 2 / 1 = 594MHz mem wr 0x01c40d14 0x8007 ; prediv = 8 mem wr 0x01c40d28 0x8000 mem wr 0x01c40d08 0x00470000 ; Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 mem wr 0x01c40d08 0x00460000 ; Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 mem wr 0x01c40d08 0x00400000 ; Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 mem wr 0x01c40d08 0x00410000 ; Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 mem wr 0x01c40d18 0x8011 ; 594/18 = 33MHz -> USB (Use AUXCLK from USB PHY Control register) mem wr 0x01c40d1c 0x8001 ; 594/2 = 297mhz -> ARM926/HDVICP(Internal) mem wr 0x01c40d60 0x8005 ; 594/6 = 99MHz -> VOICE mem wr 0x01c40d64 0x8007 ; 594/8 = 74.25Mhzv-> VENC for HD video mem or 0x01c40d38 0x0001 ; Set GOSET wait 500 mem or 0x01c40d00 0x0001 ; Enable PLL clock normal ; remove this when INIT used for multicore echo Configure DDR2 controller ; Turn on DDR2 PHY in PSC mem and 0x01c40074 0xFFFF9F3F ; PWR_DWN bit is made '0', to power the VTP module mem or 0x01c40074 0x00002000 ; Set bit CLRZ (bit 13) wait 100 mem or 0x01c40074 0x00000080; ; Set bit LOCK(bit 7) and PWRSAVE (bit 8) mem or 0x01c40074 0x00004040; ; Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) ; Disable and then re-enable DDR PSC domain wait 100 ; Step 1 - Wait for PTSTAT.GOSTAT to clear mem and 4*13+0x01C41A00 0xFFFFFFE0 ; Step 2 - Set MDCTLx.NEXT to new state mem or 4*13+0x01C41A00 1 mem or 0x01c41120 1 ; Step 3 - Start power transition ( set PTCMD.GO to 1 ) wait 100 ; Step 4 - Wait for PTSTAT.GOSTAT to clear mem and 4*13+0x01C41A00 0xFFFFFFE0 ; Step 2 - Set MDCTLx.NEXT to new state mem or 4*13+0x01C41A00 3 mem or 0x01C41120 1 ; Step 3 - Start power transition ( set PTCMD.GO to 1 ) wait 100 ; Step 4 - Wait for PTSTAT.GOSTAT to clear echo DDR2 controller initialization mem wr 0x200000E4 0x000000c5; ; External DQS gating enabled mem wr 0x20000008 0x0853C832; ; Program SDRAM Bank Config Register mem wr 0x2000000C 0x00000768; ; Program SDRAM Refresh Control Register mem wr 0x20000020 0x000000FE; ; VBUSM Burst Priority Register, pr_old_count = 0xFE mem wr 0x20000010 0x3C934B51; ; Program SDRAM Timing Control Register1 mem wr 0x20000014 0x4221C722; ; Program SDRAM Timing Control Register2 mem wr 0x20000008 0x08534832; ; Program SDRAM Bank Config Register echo Setup AEMIF (CE0 and CE1) ; EMIF configuration for J7 in NAND mode ; Use extended wait cycles to keep CE low during NAND access mem wr 0x01d10004 0xff ; Setup CE0 - 8-bit NAND, 9.26ns/cycle mem wr 0x01d10010 0x40400204; ; Setup=0, Strobe=4, Hold=0, TA=1, 8-bit mem or 0x01d10060 1; ; Setup CE1 - 16-bit normal async, 9.26ns/cycle mem wr 0x01d10014 0x00a00504 ; Setup=0, Strobe=A, Hold=0, TA=1, 8-bit mem and 0x01d10060 0xFFFFFFFD mem re 0x01d100C0 ; Clear ECC start set pc 0 ;------------------------------------------------------------------------------ ; When the RBL (Rom Boot Loader) starts, it looks for the UBL descriptor ; at page 0 from block 1. If a valid UBL is not found here, ; as determined by reading a proper UBL signature, the next block is ; searched. Searching continues for up to 24 blocks. The format of ; the descriptor is: ; Offset in the page: ; [0] 0x00 - magic word 0xA1ACEDxx ; [1] 0x04 - entry point ; [2] 0x08 - the number of pages the UBL occupies ; [3] 0x0C - start block, starting block in NAND where the UBL can be found ; [4] 0x10 - start page, the starting page within the starting block where the UBL can be found ; [5] 0x14 - load address, the application load address ; ; Note: The RBL doesn't recognize correctly the new NAND Flash devices with extended ID, but ; PEEDI has a built-in workarround ;------------------------------------------------------------------------------ [NAND_UBL] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = ubl.bin, BIN, 0x40000 AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO OOB_INFO = DM365_BOOT BURST_MODE = YES DAVINCI_UBL_DESC_TYPE = 0 DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xA1ACED00 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x100 DAVINCI_UBL_DESCRIPTOR_LOAD_ADDR = 0 DAVINCI_UBL_MAX_IMAGE_SIZE = 30*1024 ; the format of the u-boot descriptor is like the UBL one [NAND_UBOOT] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = uboot.bin, BIN, 0x320000 AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO OOB_INFO = DM365_BOOT BURST_MODE = YES DAVINCI_UBL_DESC_TYPE = 0 DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xA1ACED66 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x81080000 DAVINCI_UBL_DESCRIPTOR_LOAD_ADDR = 0x81080000 [NAND_UBOOT_ENV] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = uboot_env.bin, BIN, 0 AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO OOB_INFO = DM365_LINUX BURST_MODE = YES [NAND_KERNEL] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = uimage.bin, BIN, 0x600000 AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO OOB_INFO = DM365_LINUX BURST_MODE = YES [NAND_RAMDISK] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = ramdisk.bin, BIN, 0x900000 AUTO_ERASE = YES OOB_INFO = DM365_LINUX BURST_MODE = YES [NAND_NAND2] CPU = TMS320DM365 CHIP = NAND_FLASH DATA_BASE = 0x02004000 ; data CMD_BASE = 0x02004010 ; commands (CLE) ADDR_BASE = 0x0200400A ; addreses (ALE) FILE = "uRamdisk", BIN, 0x12400000 AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO OOB_INFO = DM365_LINUX BURST_MODE = YES [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; 2023 [TELNET] PROMPT = "dm365> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [erase_and_program_firmware] flash set 0 flash program ; ubl flash set 1 flash program ; uboot flash set 2 flash program ; uboot params flash set 3 flash program ; kernel flash set 4 flash program ; ramdisk [ACTIONS] ; user defined scripts ;AUTORUN = 1 ; executed on every target connect 1 = erase_and_program_firmware