;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : TI DaVinci TMS320DM6446 (ARM926E + DSP) ; Board : Custom board ; ; Revision : 1.0 ; ; Date : May 5, 2007 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = ARM [PLATFORM_ARM] JTAG_CHAIN = 6, 4 ; list of IR lenght of all TAP controller in JTAG chain TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 50 RESET_TYPE = ICEPICK-C, 0, 1 ; enable TAP0, warm reset CORE0 = ARM926E, 1 ; TAP 1 is DaVinci ARM926E CPU CORE0_STARTUP_MODE = RESET ; startup mode after reset: ; if RESET than no code is executed after reset ; if STOP,XX then the target executes code for XX period in ms. ; if RUN then the target executes code until stopped by the telnet "halt" command CORE0_BREAKMODE = soft ; default breakpoint mode for the debugger: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE_BREAK_PATTERN = 0xDFFFDFFF ; software breakpoint pattern JTAG_CLOCK = 1000, 20000 ; JTAG Clock in [kHz] - 5kHz jtag clock for init operations and 20MHz for normal work JTAG_TDO_DELAY = 5 CORE0_INIT=INIT_DAVINCI ; init section for DaVinci CPU CORE0_FLASH0 = NAND_UBL CORE0_FLASH1 = NAND_UBOOT CORE0_FLASH2 = NAND_UBOOT_ENV CORE0_FLASH3 = NAND_KERNEL CORE0_FLASH4 = NAND_ROOTFS CORE0_FLASH5 = NOR_FLASH CORE0_ENDIAN=little CORE0_VECTOR_CATCH_MASK = 0 ; worksapce in SRAM ;CORE0_WORKSPACE_ADDR = 0x2000 ;CORE0_WORKSPACE_LEN = 0x2000 ; length of workspace in bytes ; workspace in DDR2 CORE0_WORKSPACE_ADDR=0x80000000 CORE0_WORKSPACE_LEN=0x10000 ; length of workspace in bytes CORE0_PATH = "tftp://192.168.3.1" ; default path CORE0_FILE = "test.bin", BIN, 0x80000000 ;------------------------------------- ; init for TMS320DM6446 ;------------------------------------- [INIT_DAVINCI] ; mask all IRQs by setting all bits in the EINT default mem write 0x01c48018 0x00000000 mem write 0x01C4801C 0x00000000 ; Put the GEM in reset mem and 0x01C41A9C 0xFFFFFEFF ; Enable the Power Domain Transition Command mem or 0x01C41120 0x00000002 wait 1 ; Enable L1 & L2 Memories in Fast mode mem write 0x01C4004C 0x00000001 mem write 0x01C42010 0x00444400 ; Select the Clock Mode Depending on the value written in the Boot Table by the run script mem and 0x01C40D00 0xFFFFFEFF ; PLL2_CTL &= PLL_CLKSRC_MASK mem and 0x01C40D00 0xFFFFFFDF ; Select the PLLEN source mem and 0x01C40D00 0xFFFFFFFE ; Bypass the PLL wait 1 mem and 0x01C40D00 0xFFFFFFF7 ; Reset the PLL mem and 0x01C40D00 0xFFFFFFFD ; Power up the PLL mem and 0x01C40D00 0xFFFFFFEF ; Enable the PLL from Disable mem write 0x01C40D10 0x00000013 ; PLL2_PLLM = 0x13 wait 1 mem or 0x01C40D1C 0x00000001 ; PLL2_DIV1 wait 1 mem write 0x01C40D18 0x00000006 ; PLL2_DIV2 wait 1 mem or 0x01C40D1C 0x00080000 ; PLL2_DIV1 divider enable wait 1 mem or 0x01C40D38 0x00000001 ; PLL2_PLLCMD, GOSET=1 wait 1 mem or 0x01C40D18 0x00000001 ; PLL2_DIV2 divider enable mem or 0x01C40D38 0x00000001 ; PLL2_PLLCMD, GOSET=1 wait 1 mem or 0x01C40D00 0x00000008 ; Bring PLL out of Reset wait 1 mem or 0x01C40D00 0x00000001 ; Enable the PLL wait 1 ; Shut down the DDR2 LPSC Module mem and 0x01C41A34 0xFFFFFFE0 ; MDCTL_DDR2_0 mem or 0x01C41A34 0x00000003 ; MDCTL_DDR2_0 ; Enable the Power Domain Transition Command mem or 0x01C41120 0x000000001 ; PTCMD_0 wait 1 ; Program DDR2 MMRs for 135MHz Setting ;------------------------------------- ; Program PHY Control Register mem write 0x200000E4 0x14001905 ; DDRCTL ; Program SDRAM Bank Config Register mem write 0x20000008 0x00008622 ; SDCFG ; Program SDRAM TIM-0 Config Register mem write 0x20000010 0x229229C9 ; SDTIM0 ; Program SDRAM TIM-1 Config Register mem write 0x20000014 0x0012C722 ; SDTIM1 ; Program the SDRAM Bang Config Control Register mem write 0x20000008 0x00000622 ; SDCFG ; Program SDRAM TIM-1 Config Register mem write 0x2000000C 0x0000041D ; SDREF ; dummy DDR2 write/read mem write 0x80000000 0xA55AA55A mem read 0x80000000 ; Shut down the DDR2 LPSC Module mem and 0x01C41A34 0xFFFFFFE0 ; MDCTL_DDR2_0 mem or 0x01C41A34 0x00000001 ; MDCTL_DDR2_0 ; Enable the Power Domain Transition Command mem or 0x01C41120 0x00000001 ; PTCMD_0 wait 1 ; Turn DDR2 Controller Clocks On ; Enable the DDR2 LPSC Module mem or 0x01C41A34 0x00000003 ; MDCTL_DDR2_0 ; Enable the Power Domain Transition Command mem or 0x01C41120 0x00000001 ; PTCMD_0 wait 1 mem write 0x80010000 0x00000001 ; CFGTEST ; System PLL Intialization ; Select the Clock Mode Depending on the Value written in the Boot Table by the run script mem and 0x01C40900 0xFFFFFEFF ; PLL1_CTL ; Select the PLLEN source mem and 0x01C40900 0xFFFFFFDF ; PLL1_CTL ; Bypass the PLL mem and 0x01C40900 0xFFFFFFFE ; PLL1_CTL wait 1 ; Reset the PLL mem and 0x01C40900 0xFFFFFFF7 ; PLL1_CTL ; Disable the PLL mem or 0x01C40900 0x00000010 ; PLL1_CTL ; Power up the PLL mem and 0x01C40900 0xFFFFFFFD ; PLL1_CTL ; Enable the PLL from Disable Mode mem and 0x01C40900 0xFFFFFFEF ; PLL1_CTL ; Program the PLL Multiplier mem write 0x01C40910 0x00000015 ; PLL1_PLLM wait 1 ; Bring PLL out of Reset mem or 0x01C40900 0x00000008 ; PLL1_CTL ; Enable the PLL mem or 0x01C40900 0x00000001 ; PLL1_CTL wait 1 ; AEMIF configuration for NOR Flash (double check) mem write 0x01C40000 0x00000C1F ; PINMUX0 mem and 0x01E00014 0x3FFFFFFD ; ACFG3 mem and 0x01E00018 0x3FFFFFFD ; ACFG4 mem and 0x01E0001C 0x3FFFFFFD ; ACFG5 ;mem write 0x01E00010 0x3FFE219D ; ACF2, 16-bit NAND Flash mem write 0x01E00010 0x3FFE219C ; ACF2, 8-bit NAND Flash mem write 0x01E00060 0x00000001 ; NANDFCR, CS2 for NAND set pc 0 [NOR_FLASH] CHIP = CFI_FLASH BASE_ADDR = 0 ; User boot loader (UBL) at page 0 of block 1 ; the first page of the UBL should be an address table: ; 0x00 - magic word 0xA1ACEDxx ; 0x04 - entry point ; 0x08 - the number of pages the UBL occupies ; 0x0C - start block, starting block in NAND where the UBL can be found ; 0x10 - start page, the starting page within the starting block where the UBL can be found ; ; UBL should be programmed with hardware ECC without clean markers ; [NAND_UBL] CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ; Program UBL at page 64 if the NAND Flash has 64 pages per block and 2KB page: 64*2048 ; Program UBL at page 32 if the NAND Flash has 32 pages per block and 512B page: 32*512 ;FILE = "card:ubl.bin", BIN, 2048*64 FILE = "ubl.bin", BIN, 2048*64 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=1633,1881 ;BAD_BLOCKS=1 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = YES OOB_INFO = DAVINCI_ECC BURST_MODE=YES ; When the RBL (Rom Boot Loader) starts, it looks for the UBL descriptor ; at page 0 from block 1. If a valid UBL is not found here, ; as determined by reading a proper UBL signature, the next block is ; searched. Searching continues for up to 5 blocks ; ; Offset in the page: ; 0x00 - magic word 0xA1ACEDxx ; 0x04 - entry point ; 0x08 - the number of pages the UBL occupies ; 0x0C - start block, starting block in NAND where the UBL can be found ; 0x10 - start page, the starting page within the starting block where the UBL can be found ; 0x14 - load address, the application load address ;------------------------------------------------------------------------------ ; UBL Signatures and Special Modes ; 0xA1ACED00 - Safe boot mode ; 0xA1ACED11 - DMA boot mode ; 0xA1ACED22 - I Cache boot mode ; 0xA1ACED33 - Fast EMIF boot mode ; 0xA1ACED44 - DMA + I Cache boot mode ; 0xA1ACED55 - DMA + I Cache + Fast EMIF Safe boot mode DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xA1ACED00 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x20 DAVINCI_UBL_MAX_IMAGE_SIZE = 14*1024 ; U-BOOT at page 384 ; the first page should be an address table ; U-BOOT should be programmed with hardware ECC, without clean markers ; [NAND_UBOOT] CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ;FILE = "card:uboot.bin", BIN, 2048*384 FILE = "uboot.bin", BIN, 2048*384 ; list with bad blocks to be marked as bad ;========================================= ;BAD_BLOCKS=10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = DAVINCI_ECC BURST_MODE=YES DAVINCI_UBL_DESCRIPTOR_MAGIC = 0xA1ACED11 DAVINCI_UBL_DESCRIPTOR_ENTRY_POINT = 0x81080000 DAVINCI_UBL_DESCRIPTOR_LOAD_ADDR = 0x81080000 DAVINCI_UBL_MAX_IMAGE_SIZE = 512*1024 ; U-BOOT environment at page 256, length=64 pages, ; the U-BOOT parameters should be programmed with software ECC ; or HW6_512 without clean markers ; [NAND_UBOOT_ENV] CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) FILE = "uboot_env.bin", BIN, 2048*256 ; list with bad blocks to be marked as bad ;BAD_BLOCKS=10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = DAVINCI_ECC BURST_MODE=YES ; Linux kernel at page 512 ; the kernel should be programmed with software ECC or HW6_512, without clean markers ; [NAND_KERNEL] CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ;FILE = "card:uimage.bin", BIN, 2048*512 FILE = "uimage.bin", BIN, 2048*512 AUTO_ERASE = YES ; list with bad blocks to be marked as bad ; ;BAD_BLOCKS=10,1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 BURST_MODE=YES ; JFFS2 root filesystem, at page 44608 ; the rootfs should be programmed with hardware DAVINCI_ECC HW6_512 or ; DAVINCI_ECC HW6_512_2610 with clean markers ; [NAND_ROOTFS] CHIP = NAND_FLASH DATA_BASE = 0x02000000 ; data CMD_BASE = 0x02000010 ; commands (CLE) ADDR_BASE = 0x0200000A ; addreses (ALE) ;FILE = "tftp:uimage.bin", BIN, 0 FILE = "ftp://user:password@192.168.3.1/davinci/rootfs.jffs2", BIN, 2048*44608 ; list with bad blocks to be marked as bad ;BAD_BLOCKS=1633,1881 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = YES ;OOB_INFO = DAVINCI_ECC_HW6_512 ; Linux kernel 2.6.10 has a bug - to workaround it use: OOB_INFO = DAVINCI_ECC_HW6_512_2610 BURST_MODE=YES AUTO_ERASE = YES [SERIAL] BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "davinci> " ; telnet prompt ;BACKSPACE=127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog ; ; erase the NAND Flash ; [erase] ; erase flash flash set 0 flash erase ; ; program UBL, U-BOOT, Kernel and ROOTFS at once ; [prog] flash set 0 ; select flash profile 0 flash erase ; erase the flash flash prog ; program UBL flash set 1 ; select flash profile 1 flash program ; program U-BOOT flash set 2 ; select flash profile 2 flash program ; program U-BOOT environment flash set 3 ; select flash profile 3 flash program ; program Linux kernel flash set 4 ; select flash profile 4 flash program ; program JFFS2 root file system