Starting RedBoot v20.12.1 ...
Platform: PEEDI
FLASH TC58FVB160A: 0x05800000-0x059fffff, 32 x 0x10000 blocks

*** INFO: to enter RedBoot restart while holding both buttons pressed ***

== Executing boot script
RedBoot> fis load peedi; go
Please wait...
+++++

Network:
  IP address         : 192.168.3.101
  Subnet mask        : 255.255.255.0
  Gateway            : 192.168.3.10
  Domain Name        : office
  MAC address        : 02:00:0b:6b:30:1f


PEEDI - Powerful Embedded Ethernet Debug Interface
Copyright (c) 2005-2023 www.ronetix.at - All rights reserved
Hw:1.2, Fw:23.1005.2, SN: PD-0000-0B6B-301F
------------------------------------------------------------

peedi>
++ info: opening file 'tftp://192.168.3.5/dra821.cfg'
++ info: loading file 'tftp://192.168.3.5/dra821.cfg'...
++ info: done, loaded 6037 meaningful bytes.
++ info: opening file 'eep:license.txt'
++ info: loading file 'eep:license.txt'...
++ info: done, loaded 534 meaningful bytes.

++ info: Target Vref = 3.19V
++ info: TRST asserted
++ info: TRST released
++ info: BYPASS check passed, 1 TAP controller(s) detected
++ info: TAP: IDCODE = 0x6BA00477, AP-REG -> CORE0

#2_dra821>
++ info: TAP 0: requesting Debug and System power-up (CDBGPWRUPREQ, CSYSPWRUPREQ)
++ info: core 0: using MEM-AP port 3, ID 0x2E0002
++ info: core 0: initialized
++ debug: core 0: disable connect task
++ debug: enable connect task for core 1
++ info: core 1: using AHB port 7
++ debug: core 1: vector reset
++ info: core 1: vector catch, PC=0x000007E8, CPSR=0x01000000
++ info: core 1: Cortex-M3, CPUID = 0x412FC231
++ info: core 1: connected
++ info: start TCL script

0x80410100: 00000068

Start PLL init


0x80680008: 00FF0801


0x80680080: 00000000


0x80680080: 00008003


0x80410000: 44815C00


0x8041013C: 00000006


0x8041013C: 00000006


0x80680024: 00000001


0x80688008: 00010801


0x80688024: 00000001

PLL init done.

Run J7200 firmware

++ info: Loading image file: card:sysfw.bin
++ info: At absolute address: 0x00040000
loading at 0x40000
loading at 0x48000
loading at 0x50000
loading at 0x58000
loading at 0x60000
loading at 0x68000
loading at 0x70000
loading at 0x78000

++ info: successfully loaded 251.96 KB in 2.82 sec
setting SP = 0x00073DD8
setting PC = 0x000403C5
++ info: script execution time: 4.86 sec
++ info: script execution time: 4.90 sec
++ info: core 1: initialized
++ debug: core 1: disable connect task
++ debug: enable connect task for core 2
++ debug: core 1: enable check running task
++ info: core 2: using APB port 1
++ info: ID = 0x77040013
++ info: core 2: no FPU, no NEON
++ info: core 2: stopped by user request, PC=0x00000024, CPSR=0x000001D3
++ info: core 2: Cortex-R5, CPUID = 0x411FC153
++ info: core 2: connected
++ info: start TCL script

0x4301C0C0: 08254007

++ info: Loading image file: card:fls.elf
++ info: reading  section at vaddr: 0x41C00000 size: 0x00018960
++ info: At absolute address: 0x41C00000
loading at 0x41C00000
loading at 0x41C08000
loading at 0x41C10000
++ info: skipping section at vaddr: 0x41C18980 size: 0x0
++ info: reading  section at vaddr: 0x41C1DD00 size: 0x000072F8
loading at 0x41C18000
++ info: skipping section at vaddr: 0x41C24FF8 size: 0x0
++ info: reading  section at vaddr: 0x41C29C28 size: 0x00006000
loading at 0x41C1DD00
++ info: reading  section at vaddr: 0x41C2FC80 size: 0x00002460
loading at 0x41C29C28
++ info: reading  section at vaddr: 0x41C32100 size: 0x00000400
loading at 0x41C2FC80
++ info: reading  section at vaddr: 0x41C32900 size: 0x00000AE0
loading at 0x41C32100
++ info: skipping section at vaddr: 0x41C79000 size: 0x0
++ info: reading  section at vaddr: 0x41C7E000 size: 0x00002000
loading at 0x41C32900
++ info: reading  section at vaddr: 0x41CE3000 size: 0x00000040
loading at 0x41C7E000
loading at 0x41CE3000

++ info: successfully loaded 171.96 KB in 0.93 sec
++ info: script execution time: 0.96 sec
++ info: core 2: initialized
++ debug: core 2: enable detect reset
++ debug: core 2: disable connect task
++ debug: core 2: enable check running task

#2_dra821>
CORE2 -> Cortex-R5 - stopped by breakpoint
         PC=0x41C1819C, CPSR=0x6000011F

#2_dra821> flash info

FLASH configuration for core #2:
  CPU: TI_J7200
  Device: S28HS512T    ID: 0x34 0x5B 0x1A 0x0F 0x03 0x90
  3-BYTE command set, Fast Read, 32-bit addressing
  Chip size: 64 MB
  Write chunk size: 256 bytes
  Erase chunk size: 64 KB

FLASH commands default parameters:
  flash read   0x00000000 0x04000000
  flash blank  0x00000000 0x04000000
  flash erase  0x00000000 0x04000000
  flash lock   0x00000000 0x04000000
  flash unlock 0x00000000 0x04000000
  flash query  0x00000000 0x04000000
  flash program test32k.bin bin 0x00100000
  flash verify  test32k.bin bin 0x00100000
  flash multi program #0 #1 #2 test32k.bin bin 0x00100000
  flash multi erase #0 #1 #2 0x00000000 0x04000000
#2_dra821> flash erase 0x100000
erasing     at 0x00100000 (block #16)
++ info: successfully erased 64 KB in 0.99 sec

#2_dra821> flash program
++ info: Programming image file: tftp://192.168.3.60/test32k.bin
++ info: Programming using agent, buffer = 59904 bytes
++ info: At absolute address:    0x00100000
programming at 0x00100000
programming at 0x00107400

++ info: successfully programmed 32 KB in 0.77 sec

#2_dra821> flash verify
++ info: Verifying image file: tftp://192.168.3.60/test32k.bin
++ info: At absolute address:  0x00100000
verifying at 0x00100000

++ info: successfully verified 32 KB in 0.25 sec
#2_dra821>