;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : AM3517 ; Supported board : Custom board ; ; Revision : 1.0 ; ; Date : 23.11.2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 6, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 10000 ; JTAG Clock in [kHz] ;JTAG_TDO_DELAY = AUTO TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 ; time in ms between releasing the reset and starting the jtag communication RESET_TYPE = ICEPICK-C, 3, 1 ; enable TAP3, warm reset CORE0 = Cortex-A, 1 ; TAP is OMAP3530 CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_BOARD ; init section for NOR programming without U-BOOT ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT CORE0_FLASH0 = NOR_FLASH ; FLASH section parameters CORE0_FLASH1 = NAND_XLOAD ; FLASH section parameters CORE0_FLASH2 = NAND_UBOOT ; FLASH section parameters CORE0_WORKSPACE = 0x40200000, 0x10000 ; address, length in bytes ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "pattern_1M.bin", BIN, 0x80000000 [INIT_BOARD] ; set address and data bus to mode 0 memory write 0x48002078 0x01080100 ;CONTROL_PADCONF_SDRC_DQS3: a1 to mode 0 (MSB) memory write 0x4800207C 0x01080108 ;CONTROL_PADCONF_GPMC_A2: a3, a2 to mode 0 memory write 0x48002080 0x01080108 ;CONTROL_PADCONF_GPMC_A4: a5, a4 to mode 0 memory write 0x48002084 0x01080108 ;CONTROL_PADCONF_GPMC_A6: a7, a6 to mode 0 memory write 0x48002088 0x01080108 ;CONTROL_PADCONF_GPMC_A8: a9, a8 to mode 0 memory write 0x4800208C 0x01080108 ;CONTROL_PADCONF_GPMC_A10: d0, a10 to mode 0 memory write 0x48002090 0x01080108 ;CONTROL_PADCONF_GPMC_D1: d2, d1 to mode 0 memory write 0x48002094 0x01080108 ;CONTROL_PADCONF_GPMC_D3: d4, d3 to mode 0 memory write 0x48002098 0x01080108 ;CONTROL_PADCONF_GPMC_D5: d6, d5 to mode 0 memory write 0x4800209C 0x01080108 ;CONTROL_PADCONF_GPMC_D7: d8, d7 to mode 0 memory write 0x480020A0 0x01080108 ;CONTROL_PADCONF_GPMC_D9: d10, d9 to mode 0 memory write 0x480020A4 0x01080108 ;CONTROL_PADCONF_GPMC_D11: d12, d11 to mode 0 memory write 0x480020A8 0x01080108 ;CONTROL_PADCONF_GPMC_D13: d14, d13 to mode 0 memory write 0x480020AC 0x01180108 ;CONTROL_PADCONF_GPMC_D15: ncs0, d15 to mode 0 memory write 0x480020B0 0x01180118 ;CONTROL_PADCONF_GPMC_NCS1: ncs2, ncs1 to mode 0 memory write 0x480020C0 0x01180118 ;CONTROL_PADCONF_GPMC_NADV_ALE: memory write 0x480020C4 0x01180118 ;CONTROL_PADCONF_GPMC_NWE: memory write 0x480020C8 0x0118010C ;CONTROL_PADCONF_GPMC_NBE1: gpmc_nwp to mode 0, gpmc_nbe1 to mode 4 (GPIO61=NOR_WP#), pull-down enabled ;memory write 0x480020C8 0x0118011F ;CONTROL_PADCONF_GPMC_NBE1: gpmc_nwp to mode 0, gpmc_nbe1 to mode 7 (safe mode), pull-up enabled memory write 0x480020CC 0x01080108 ;CONTROL_PADCONF_GPMC_WAIT0: wait1, wait0 to mode 0 ; Protection Module Register Target APE (PM_RT) memory write 0x68010068 0xFFFFFFFF ;RT_REQ_INFO_PERMISSION_1, UNLOCK_1 memory write 0x68010050 0xFFFFFFFF ;RT_READ_PERMISSION_0, UNLOCK_1 memory write 0x68010058 0xFFFFFFFF ;RT_WRITE_PERMISSION_0, UNLOCK_1 memory write 0x68010060 0x00000000 ;RT_ADDR_MATCH_1, UNLOCK_2 memory write 0x68012448 0x0000FFFF ;GPMC_REQ_INFO_PERMISSION_0, UNLOCK_3 memory write 0x68012450 0x0000FFFF ;GPMC_READ_PERMISSION_0, UNLOCK_3 memory write 0x68012458 0x0000FFFF ;GPMC_WRITE_PERMISSION_0, UNLOCK_3 memory write 0x68012848 0x0000FFFF ;OCM_REQ_INFO_PERMISSION_0, UNLOCK_3 memory write 0x68012850 0x0000FFFF ;OCM_READ_PERMISSION_0, UNLOCK_3 memory write 0x68012858 0x0000FFFF ;OCM_WRITE_PERMISSION_0, UNLOCK_3 memory write 0x68012880 0x00000000 ;OCM_ADDR_MATCH_2, UNLOCK_2 memory write 0x6C000048 0xFFFFFFFF ;SMS_RG_ATT0, UNLOCK_1 ; init peripheral clocks memory write 0x48005000 0x0003FFFF ;CM_FCLKEN_PER memory write 0x48005010 0x0003FFFF ;CM_ICLKEN_PER ; now set GPIO2 unit to defaults memory write 0x49050010 0x00000010 ;GPIO_SYSCONFIG: no-idle, wakeup disabled, normal mode, clock free running memory write 0x49050030 0x00000002 ;GPIO_CTRL: GATINGRATIO FCLK = ICLK/2, Module is enabled, clocks are not gated ; now set GPIO61 high to release NOR_WP# memory write 0x49050034 0xDFFFFFFF ;GPIO_OE: GPIO port is configured as output if 0x0 memory write 0x4905003C 0x20000000 ;GPIO_DATAOUT: GPIO is set if 0x1 (set GPIO61 = high) memory write 0x49050094 0x20000000 ;GPIO_SETDATAOUT: set the pin with 0x1 (set pin T1 (GPIO61)) ; init GPMC memory write 0x6E000010 0x00000010 ;GPMC_SYSCONFIG: no-idle memory write 0x6E00001C 0x00000000 ;GPMC_IRQENABLE: mask all interrupts memory write 0x6E000040 0x00000000 ;GPMC_TIMEOUT_CONTROL: no timeouts memory write 0x6E000050 0x00000010 ;GPMC_CONFIG: all WAIT1, WAIT0 polarity active low, WP=high, no limited address, do not force posted write ; reset all cs areas memory write 0x6E000078 0x00000000 ;GPMC_CONFIG7_0 memory write 0x6E0000A8 0x00000000 ;GPMC_CONFIG7_1 memory write 0x6E0000D8 0x00000000 ;GPMC_CONFIG7_2 memory write 0x6E000108 0x00000000 ;GPMC_CONFIG7_3 memory write 0x6E000138 0x00000000 ;GPMC_CONFIG7_4 memory write 0x6E000168 0x00000000 ;GPMC_CONFIG7_5 memory write 0x6E000198 0x00000000 ;GPMC_CONFIG7_6 memory write 0x6E0001C8 0x00000000 ;GPMC_CONFIG7_7 ; init NOR at cs0 ;fast timing ;memory write 0x6E000060 0x00001200 ;GPMC_CONFIG1_0: asynchronous R/W, WAIT0, 16Bit, NOR Flash device ;memory write 0x6E000064 0x00001001 ;GPMC_CONFIG2_0: CSRW/RD-OFFTIME=16 GPMC_FCLK cycles, CSONTIME=1 GPMC_FCLK cycle ;memory write 0x6E000068 0x00000201 ;GPMC_CONFIG3_0: ADVWR/RD-OFFTIME=2 GPMC_FCLK cycles, ADV-ONTIME=1 GPMC_FCLK cycle ;memory write 0x6E00006C 0x0F031003 ;GPMC_CONFIG4_0: WE/OE-OFFTIME=15/16 GPMC_FCLK cycles, WE/OE-ONTIME=3/3 GPMC_FCLK cycle ;memory write 0x6E000070 0x000F1111 ;GPMC_CONFIG5_0: RDACCESSTIME=15 GPMC_FCLK cycles, WR/RD-CYCLETIME=17 GPMC_FCLK cycles ;memory write 0x6E000074 0x000004C4 ;GPMC_CONFIG6_0: WRACCESSTIME=31 GPMC_FCLK cycles, WRDATAONADMUXBUS=15th GPMC_FCLK cycle, ; CYCLE2CYCLEDELAY=10 GPMC_FCLK cycles; add same delay between two accesses ;memory write 0x6E000078 0x00000848 ;GPMC_CONFIG7_0: MASKADDRESS=128MBytes, CS enabled, BASEADDRESS=0x08000000 ;slow timing memory write 0x6E000060 0x00001200 ;GPMC_CONFIG1_1: asynchronous R/W, WAIT0, 16Bit, NOR Flash device ; CYCLE2CYCLEDELAY=10 GPMC_FCLK cycles; add same delay between two accesses memory write 0x6E000064 0x001F1F01 ;GPMC_CONFIG2_1: CSRW/RD-OFFTIME=31 GPMC_FCLK cycles, CSONTIME=1 GPMC_FCLK cycle memory write 0x6E000068 0x00080803 ;GPMC_CONFIG3_1: ADVWR/RD-OFFTIME=8 GPMC_FCLK cycles, ADV-ONTIME=3 GPMC_FCLK cycle memory write 0x6E00006C 0x1D091D09 ;GPMC_CONFIG4_1: WE/OE-OFFTIME=29/29 GPMC_FCLK cycles, WE/OE-ONTIME=9/9 GPMC_FCLK cycle memory write 0x6E000070 0x041D1F1F ;GPMC_CONFIG5_1: RDACCESSTIME=29 GPMC_FCLK cycles, WR/RD-CYCLETIME=31 GPMC_FCLK cycles memory write 0x6E000074 0x1D0904C4 ;GPMC_CONFIG6_1: WRACCESSTIME=29 GPMC_FCLK cycles, WRDATAONADMUXBUS=9th GPMC_FCLK cycle, ; CYCLE2CYCLEDELAY=4 GPMC_FCLK cycles; add same delay between two accesses memory write 0x6E000078 0x00000848 ;GPMC_CONFIG7_1: MASKADDRESS=128MBytes, CS enabled, BASEADDRESS=0x10000000 ; init 8Bit NAND attached to CS1 (eSOM/3517 NOR boot configuration) memory write 0x6E000090 0x00010800 ;GPMC_CONFIG1_I: 8Bit, NAND Flash device memory write 0x6E000094 0x00141400 ;GPMC_CONFIG2_I: CSRW/RD-OFFTIME=20 GPMC_FCLK cycles memory write 0x6E000098 0x00141400 ;GPMC_CONFIG3_I: ADVWR/RD-OFFTIME=20 GPMC_FCLK cycles memory write 0x6E00009C 0x0F010F01 ;GPMC_CONFIG4_I: WE/OE-OFFTIME=15 GPMC_FCLK cycles, WE/OE-ONTIME=1 GPMC_FCLK cycle memory write 0x6E0000A0 0x010C1414 ;GPMC_CONFIG5_I: PAGEBURSTACCESSTIME=1 GPMC_FCLK cycle, RDACCESSTIME=12 GPMC_FCLK cycles, ; WR/RD-CYCLETIME=20 GPMC_FCLK cycles memory write 0x6E0000A4 0x1F0F0A80 ;GPMC_CONFIG6_I: WRACCESSTIME=31 GPMC_FCLK cycles, WRDATAONADMUXBUS=15th GPMC_FCLK cycle, ; CYCLE2CYCLEDELAY=10 GPMC_FCLK cycles; add same delay betweebn two accesses memory write 0x6E0000A8 0x00000870 ;GPMC_CONFIG7_I: MASKADDRESS=128MBytes, CS enabled, BASEADDRESS=0x30000000 ; following is dumped from the CPU ROM bootloader memory write 0x48004c00+16 0x20 ; WKUP_CM: CM_ICLKEN_WKUP memory write 0x48004c00 0x20 ; CM_FCLKEN_WKUP memory write 0x48314000+16 2 ; WDTIMER2: WD_SYSCONFIG memory write 0x4800291c 0 ; SDRC module semaphore memory write 0x48004c10 0x24 ; WKUP_CM: CM_ICLKEN_WKUP memory write 0x48004000+3328 0x110015 ; CM_CLKEN_PLL memory write 0x48004000+3328 0x110015 ; CM_CLKEN_PLL memory write 0x48004000+2308 0x15 ; CM_CLKEN_PLL_MPU memory write 0x48307000+624 0x40 ; Power and reset manager Module region A memory write 0x48306000+3392 3 memory write 0x48005000+320 0x2030a50 ; PER_CM memory write 0x48004000+2624 0x40a ; CORE_CM memory write 0x48004000+3136 0x4 ; WKUP_CM memory write 0x48004d00 0x310030 ; Clock_Control_Reg_CM memory write 0x48004d00+48 0 memory write 0x48004d00+68 0x6019 memory write 0x48004d00+72 2 memory write 0x48004000+3328 0x370030 memory write 0x48004904 0x35 ; MPU_CM memory write 0x48004904+48 0 memory write 0x48004904+60 0x100000 memory write 0x48004904+64 1 memory write 0x48004904+68 0 memory write 0x48004000+3328 0x300035 ; Clock_Control_Reg_CM memory write 0x48004000+3376 0 memory write 0x48004000+3392 0x8c01900 memory write 0x48004000+3328 0x300037 memory write 0x48200000+80 0 ; MPU INTC memory write 0x48200000+72 0 memory write 0x48200000+140 0xffffffff memory write 0x48200020+140 0xffffffff memory write 0x48200040+140 0xffffffff memory write 0x48200000+72 1 m w16 0x48002000+530 0 ; System control module memory write 0x48002000+1436 0x6ff memory write 0x5c040000+4 1 ; IVA2.2 memory write 0x48002000+1436 0x6fe ; System control module memory write 0x48002580+28 0x7aa memory write 0x48002580 0xf00b7a2 memory write 0x48002580 0xf0037a2 memory write 0x48002580 0xf00b7a2 memory write 0x48002580 0xf00b7a2 memory write 0x48002580 0xf00b7a2 ;... memory write 0x48002580 0xf00b0a2 memory write 0x48002580 0xf00b722 memory write 0x48002580 0xf00b7a2 memory write 0x48004a10+32 8 ; Clock_Control_Reg_CM memory write 0x48004a10 0x5a memory write 0x48002000 0x7ef m w16 0x480021bc 0x118 m w16 0x480021ba 0x118 memory write 0x48004a00 0x8000 ;memory write 0x48004a16 0x805a memory write 0x48314000+72 0xaaaa ; Disable WDT2 memory write 0x48314000+72 0x5555 [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 20000 stop break del all beep 100 100 [NOR_FLASH] CHIP = M29W640FB ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0x08000000 ; chip is mapped at 0x08000000 FILE = "test2m.bin" bin 0x08000000 AUTO_ERASE = YES ; erase before program AUTO_LOCK = NO ; lock after program [NAND_XLOAD] CHIP = NAND_FLASH CMD_BASE = 0x6E0000AC ADDR_BASE = 0x6E0000B0 DATA_BASE = 0x6E0000B4 ERASE_BAD_BLOCKS = NO OOB_INFO = OMAP3_ECC BURST_MODE = NO FILE = "xload.bin" 0 [NAND_UBOOT] CHIP = NAND_FLASH CMD_BASE = 0x6E0000AC ADDR_BASE = 0x6E0000B0 DATA_BASE = 0x6E0000B4 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 BURST_MODE = NO FILE = "flash-uboot.bin" 0x80000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "AM3517> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog