;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : ATSAMA5D33, ATSAMA5D35 ; Supported board : SAMA5D3x-CM ; ; Revision : 2.0 ; ; Date : January 04, 2016 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ; Important! ; The JTAG Interface of ATSAMA5 is disabled after power up. ; To ensure a proper connection use the following procedure: ; - power-up (or make a reset) with CS_BOOT = 0. Make sure that ; no USB cable is connected. ; The "RomBOOT" prompt should appear in the serial debug ; console of the board. ; - hit a 'x' in the debug console ; PEEDI will connect normally. ; ; ; ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is CortexA8 [PLATFORM_Cortex-A] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 20000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 0 ; length of RESET pulse in ms; 0 means no RESETx VERBOSE_INFO = 1 ; print info if CORE0_DEBUG_ADDR is not defined CORE0 = Cortex-A, 0, 0xBA00477 ; TAP is ATSAMA5D3x CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = SAMA5-INIT ; init section for NAND programming without U-BOOT ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT CORE0_FLASH0 = PMECC_BOOTSTRAP CORE0_FLASH1 = PMECC_U-BOOT CORE0_FLASH2 = PMECC_LINUX CORE0_FLASH3 = PMECC_ROOTFS CORE0_FLASH4 = NOR_FLASH CORE0_FLASH5 = SPI_FLASH CORE0_WORKSPACE = 0x300000, 0x20000 ; address, lenght in bytes ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1/sama5d3x/images" CORE0_FILE = "", BIN, 0x20000000 [INIT_LINUX] break add hard 0xc0361310 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 60000 stop break del all beep 100 100 [SAMA5-INIT] mem write 0xFFFFFE08 0xA5000001 ; Allow user reset mem write 0xFFFFFE44 0x3FFFAFFF ; Disable watchdog ; enable all preripherals mem write 0xFFFFFC00 0xFFFFFFFF ; PMC_SCER mem write 0xFFFFFC10 0xFFFFFFFF ; PMC_PCER0 mem write 0xFFFFFD00 0xFFFFFFFF ; PMC_PCER1 mem write 0xfffffc30 0x00001121 ; Switch to external crystal oscillator wait 10 echo Perform PLLA initialization! mem write 0xFFFFFC80 0x00000300 ; Recommended by Atmel to work properly when the chip get hot- 30.05.2013 mem write 0xfffffc28 0x00000000 mem write 0xfffffc28 0x215C3F01 ; Fcpu=530MHz, Fddr=133MHz wait 10 mem write 0xfffffc30 0x00001201 wait 10 mem write 0xfffffc30 0x00001202 wait 10 clock normal ; enable NAND controller mem write 0xffffc010 0xffffffff mem write 0xfffffd0c 0x10001005 mem write 0xffffc004 0x00000001 mem write 0xffffc63c 0x02030203 mem write 0xffffc640 0x09060906 mem write 0xffffc644 0x00120012 mem write 0xffffc648 0x88050585 mem write 0xffffc64c 0x00000003 mem write 0xffffc000 0x007f2000 mem write 0xffffc018 0x00000000 mem write 0xffffc084 0x00000001 mem write 0xffffc084 0x00000010 mem write 0xffffc070 0x00100000 echo Perform DDR2 initialization! mem write 0xfffffD00 0x00020000 ; enable ddr2 clock mem write 0xFFFFFC00 0x00000004 mem write 0xFFFFEA78 0x01010001 ; Init the special register for sama5d3x. MPDDRC DLL Slave Offset Register - DDR2 configuration mem write 0xFFFFEA74 0xC5011F07 ; MPDDRC DLL Master Offset Register mem write 0xFFFFEA34 0x00000404 ; MPDDRC I/O Calibration Register mem write 0xFFFFEA20 0x00000006 ; Step 1: Program the memory device type into the Memory Device Register mem write 0xFFFFEA08 0x00F2003D ; Step 2: Program the feature of DDR2-SDRAM device into the Timing Register, and into the Configuration Register mem write 0xFFFFEA0C 0x22228226 mem write 0xFFFFEA10 0x02C81C1A mem write 0xFFFFEA14 0x00072278 mem write 0xFFFFEA00 0x00000001 ; Step 3: An NOP command is issued to the DDR2-SDRAM mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000001 ; Step 4: An NOP command is issued to the DDR2-SDRAM mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000002 ; Step 5: An all banks precharge command is issued to the DDR2-SDRAM. mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000005 ; Step 6 mem write 0x20002000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000005 ; Step 7 mem write 0x20003000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000005 ; Step 8 mem write 0x20001000 0x00000000 ; base_address | (1<<12) wait 5 mem or 0xFFFFEA08 0x00000080 ; Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset) mem write 0xFFFFEA00 0x00000003 ; Step 10 mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000002 ; Step 11: An all banks precharge command is issued to the DDR2-SDRAM. mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000004 ; Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register mem write 0x20000000 0x00000000 wait 5 mem write 0xFFFFEA00 0x00000004 ; Set 2nd CBR mem write 0x20000000 0x00000000 wait 5 mem and 0xFFFFEA08 0xFFFFFF7F ; Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset). mem write 0xFFFFEA00 0x00000003 ; Step 14: mem write 0x20000000 0x00000000 wait 5 mem or 0xFFFFEA08 0x00007000 ; Step 15: Program OCD field into the Configuration Register to high (OCD calibration default). wait 5 mem write 0xFFFFEA00 0x00000005 ; Step 16 mem write 0x20001000 0x00000000 ; base_address | (1<<12) wait 5 mem and 0xFFFFEA08 0xFFFF8FFF ; Step 17 wait 5 mem write 0xFFFFEA00 0x00000005 ; Step 18 mem write 0x20001000 0x00000000 ; base_address | (1<<12) wait 5 mem write 0xFFFFEA00 0x00000000 ; Step 19: A Nornal mode command is provided. mem write 0x20000000 0x00000000 mem write 0x20000000 0x00000000 ; Step 20: Perform a write access to any DDR2-SDRAM address mem write 0xFFFFEA04 0x00000411 ; Step 21: Write the refresh rate into the count field in the Refresh Timer register. wait 5 echo NOR Flash mem write 0xFFFFC600 0x00020001 mem write 0xFFFFC604 0x0b0a0b0a mem write 0xFFFFC608 0x000e000b mem write 0xFFFFC60C 0x00000000 mem write 0xFFFFC610 0x00011003 echo Enable the REMAP of SRAM to address 0x00000000 memory write 0x00800000 0x00000001 ; AXIMX_REMAP memory write 0xFFFFED00 0x00000001 ; MATRIX_MRCR [PMECC_BOOTSTRAP] CHIP = NAND_FLASH CMD_BASE = 0x60400000 ADDR_BASE = 0x60200000 DATA_BASE = 0x60000000 FILE = "boot.bin", 0x00 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC NUM_ECC = 8 CPU = ATSAMA5 HEADER = YES [PMECC_U-BOOT] CHIP = NAND_FLASH CMD_BASE = 0x60400000 ADDR_BASE = 0x60200000 DATA_BASE = 0x60000000 FILE = "u-boot.bin", BIN, 0x40000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC NUM_ECC = 8 CPU = ATSAMA5 HEADER = NO [PMECC_LINUX] CHIP = NAND_FLASH CMD_BASE = 0x60400000 ADDR_BASE = 0x60200000 DATA_BASE = 0x60000000 FILE = "sama5d3xek.itb", BIN, 0x300000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC NUM_ECC = 8 CPU = ATSAMA5 HEADER = NO [PMECC_ROOTFS] CHIP = NAND_FLASH CMD_BASE = 0x60400000 ADDR_BASE = 0x60200000 DATA_BASE = 0x60000000 FILE = "rootfs.ubi", BIN, 0x00F80000 CS_ASSERT = 0xFFFFFA34, 0x0010 CS_RELEASE = 0xFFFFFA30, 0x0010 ERASE_BAD_BLOCKS = NO OOB_INFO = AT91_PMECC NUM_ECC = 8 CPU = ATSAMA5 HEADER = NO ; Test NAND Flash and mark the bad blocks [NAND_TEST] flash area delete ; delete all test regions flash area add 0x00000000 1024*512 ; define test area flash area add 0x00040000 1024*1024*15 ; define test area flash area list ; list all defined areas flash area test ; start testing of all test areas ; flash area test markbad ; start testing and mark bad blocks [SPI_FLASH] CHIP = SPI25_FLASH ; the DataFlash chip will be autodetected CPU = ATSAMA5D3 SPI_DIV = 8 nSPI = 0 ; which SPI controller: 0 or 1 nCS = 0 ; which chip select: 0 - 3 SPI_SPCK = PIOD, A, 12 ; pin definition for SPCK: PIOD, peripheral A SPI_MISO = PIOD, A, 10 ; pin definition for MISO: PIOD, peripheral A SPI_MOSI = PIOD, A, 11 ; pin definition for MOSI: PIOD, peripheral A SPI_CS = PIOD, A, 13 ; pin definition for CS : PIOD, peripheral A FILE = "test.bin", BIN, 0 [NOR_FLASH] CHIP = CFI_FLASH ACCESS_METHOD = AGENT CHIP_WIDTH = 16 CHIP_COUNT = 1 BASE_ADDR = 0x10000000 FILE = "test32k.bin", BIN, 0x10000000 AUTO_ERASE = NO [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "sama5d3x> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts 1 = prog [prog] flash set 0 ; Bootstrap flash erase flash program flash set 1 flash prog u-boot.bin bin 0x000C0000 ; u-boot first image flash prog u-boot.bin bin 0x00140000 ; u-boot second image ; Program Kernel flash set 2 flash prog sama5d3xek.itb bin 0x00300000 ; kernel first image flash prog sama5d3xek.itb bin 0x00980000 ; kernel second image [rootfs] flash set 3 ; rootfs flash prog rootfs.ubi bin 0x00F80000