;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; eCosCentric based on original by Ronetix GmbH ; ; Supported devices : Altera Cortex-A9 HPS ; Supported board : Cyclone V SX ; ; Revision : 1.0 ; ; Date : 2013-05-01 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2012, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;FILE = tftp://10.0.1.1/licenses.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is Cortex-A [PLATFORM_Cortex-A] JTAG_CHAIN = 4,4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] - MAX 5000 to operate properly with phys mem TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET VERBOSE_INFO = 0 ; print info if CORE0_DEBUG_ADDR is not defined CORE0 = cortex-a, 0, 0x4BA00477 ; TAP is Cortex-A CPU CORE0_DEBUG_ADDR = 0x80110000, 0x80118000 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_CYCLONE5 ; init section with working U-BOOT CORE0_WORKSPACE = 0xffff0000, 0x8000 ; address, length in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.1.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.1.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" ;CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_CYCLONE5] ; Write to the clock manager to prevent the system from gating the debug clocks during a warm reset mem wr 0xffd04010 1 ; disable Watchdog - Toggle RESET in PERMODRST mem or 0xffd05014 0x40 mem and 0xffd05014 0xFFFFFFBF ; initialize DDR at 0x01000000 using u-boot-spl [INIT_DDR] ; Load SPL into SRAM - initialize the targets DDR memory mem load u-boot-spl-cyclone5.bin bin 0xffff0000 mem verify u-boot-spl-cyclone5.bin bin 0xffff0000 breakpoint add hard 0xffff0a38 go 0xffff0000 wait 3000 stop breakpoint delete all mem test 0x010000 1024*1024 [INIT_LINUX] break add hard 0x804bd50c ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 30000 stop beep 100 100 break del all [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "Cyclone_V> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume ; EOF