;-------------------------------------------------------------------------- ; ; PEEDI target configuration file ; ; Ronetix GmbH ; ; Supported devices : DRA821U, J7200 ; Supported board : TI J7200XSOMXEVM ; ; The BOOT mode should be: NO BOOT ; The ELF files should be stored on a MMC/SD card ; ; SW8 SW9 ; 1000-1000 0111-0000 - NO-BOOT ; 0000-0000 0100-0000 - QSPI boot ; 1000-0010 0000-0000 - MMC/SD boot ; ; Board fotos: ; http://download.ronetix.at/peedi/cfg_examples/download/dra821 ; ; Cortex-R5: 0x41010000 64KB SRAM ; Cortex-R5: 0x41C00000 512KB SRAM ; ; The SoC initialization process: ; - PEEDI connects to DAP, AP3 (core 0) and enables the communication with ; DMSC (Cortex-M3) ; ; - PEEDI connects to Cortex-M3 (core 1), initialize ATCM, RAT and PLL ; - PEEDI loads and executes the System Firmware ; - now Cortex-R5 (core 2) is enabled and PEEDI connects. ; - PEEDI loads and executes fls_peedi_mcu1_0_release.xer5f, which ; makes some additional initializations: PLL and PinMux. ; fls_peedi_mcu1_0_release.xer5f is prepared by Ronetix based on: ; ti-processor-sdk-rtos-j7200-evm-08_04_00_02/mcusw/mcal_drv/mcal/examples/Fls/fls_app ; ; Installation steps: ; 1. Set the BOOT mode to NO-BOOT ; ; 2. Prepare a FAT formated SD card ; ; 3. Download TI J7200 system firmware (ti-fs-firmware-j7200-gp.bin): ; https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/tree/ti-sysfw?h=ti-linux-firmware ; or ; http://download.ronetix.at/peedi/cfg_examples/download/dra821/ti-fs-firmware-j7200-gp.bin ; ; 4. Copy to SD card and rename to "sysfw.bin" because PEEDI supports ; only 8+3 file names ; ; 5. Download TI J7200 init application: ; http://download.ronetix.at/peedi/cfg_examples/download/dra821/fls_peedi_mcu1_0_release_strip.xer5f ; ; 6. Copy to SD card and rename to "fls.elf" ; ; 7. Connect PEEDI and power up the board. ; ; 8. Check the connection log: ; http://download.ronetix.at/peedi/cfg_examples/download/dra821/boot.log ; ; Date: September 06, 2022 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = CORTEX [PLATFORM_CORTEX] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1500 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 0 ; length of RESET pulse in ms; 0 means no RESET CORE0 = AP-REG, 0, 0x6BA00477 CORE0_APSEL = 3 ; access port CORE0_INIT = INIT_MEM_AP CORE1 = CORTEX-M ; Cortex-M3 CORE1_APSEL = 7 CORE1_STARTUP_MODE = RESET CORE1_INIT = INIT_M3 CORE1_ENDIAN = LITTLE ; core is little endian CORE1_BREAKMODE = SOFT ; breakpoint mode CORE1_WORKSPACE = 0x40000, 0x8000 ; address, length in bytes CORE1_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE1_PATH = "tftp://192.168.3.5/dra821" CORE2 = Cortex-A ; Cortex-R5 CORE2_APSEL = 1 CORE2_DEBUG_ADDR = 0x9d010000, 0x9d018000 ; CoreSight Debug component CORE2_STARTUP_MODE = RESET CORE2_INIT = INIT_R5.tcl CORE2_ENDIAN = LITTLE CORE2_WORKSPACE = 0x41010000, 0x10000 ; SRAM 64KB CORE2_FLASH0 = FLASH_SPI CORE2_PATH = "tftp://192.168.3.5/dra821" ; comment out the '[]' in order to connect to both Cortex-A72 [] CORE3 = Cortex-ARMv8_AMP ; Cortex-A72 CORE3_APSEL = 1 CORE3_DEBUG_ADDR = 0x90410000, 0x90420000 ; CoreSight Debug component CORE3_STARTUP_MODE = RESET CORE3_WORKSPACE = 0x41010000, 0x10000 ; SRAM 64KB CORE4 = Cortex-ARMv8_AMP ; Cortex-A72 CORE4_APSEL = 1 CORE4_DEBUG_ADDR = 0x90510000, 0x90520000 CORE4_STARTUP_MODE = RESET CORE4_WORKSPACE = 0x41010000, 0x10000 ; SRAM 64KB [INIT_MEM_AP] mem write 0xF0 0x00190000 mem write 0x44 0x00102098 [INIT_M3] ; Enable ATCM: Configuring ATCM for the R5Fs mem write 0x45A50100 0x888 ; MCU Cluster Core 0 mem write 0x45A50180 0x888 ; MCU Cluster Core 1 mem write 0x45A40100 0x888 ; Main Cluster Core 0 mem write 0x45A40180 0x888 ; Main Cluster Core 1 ; Configure the RAT for view into the SoC ; enable and set region size for first two regions mem write 0x44200024 0x80000000 ; If the M3 reads from here -> IN ADDRESS mem write 0x44200028 0x00000000 ; the RAT will retrieve data from here -> OUT ADDRESS mem write 0x4420002C 0x00000000 ; Upper 16 bits of the real physical address. mem write 0x44200020 0x8000001D mem write 0x44200044 0x60000000 ; IN ADDRESS mem write 0x44200048 0x40000000 ; OUT ADDRESS mem write 0x4420004C 0x00000000 ; Upper 16 bits of the real physical address. mem write 0x44200040 0x8000001D ; Put all R5Fs in HALT mode upon PORz by writing to the MMRs. mem write 0x45A50120 1 mem write 0x45A501A0 1 mem write 0x45A40120 1 mem write 0x45A401A0 1 run $pll.tcl [pll.tcl] set addr 0x80410100 mon "memory read $addr" set val [mrw $addr] # check if PLL already initialized if {== $val 0x68} \ {mon {run $m3_init}} \ {puts "Skip PLL initialization"} [m3_init] echo Start PLL init ; Unlocked PLL MMRs. mem write 0x80680010 0x68EF3490 mem write 0x80680014 0xD172BC5A ; Read configuration MMRs. mem read 0x80680008 ; returns 0x00FF0801 ; temp value (HSDIV_Presence) = 0x000000FF ; HSDIV presence value = 0x000000FF ; Number of hsidvs: 8 ; Parsed PLL configuration information. ; Note: deskew PLL programming isn't implemented yet ; This is a fractional PLL with calibration functionality. ; For debugging: ; Base address: 0x00680000 ; PLL index: 0x00000000 ; PLL index register base: 0x00000000 ; Register: 0x00000020 ; Clocking scheme: 0 ; Set PLL to external bypass via Control MMR. mem and 0x80680020 0x7FFFFFFF mem or 0x80680020 0x80000000 mem and 0x80680020 0xFFFF7FFF ; Disabled PLL mem and 0x80680020 0xFFFFFFFE mem or 0x80680020 0x00000001 ; Enabled noise-cancelling DAC. mem and 0x80680020 0xFFFFFFFD mem or 0x80680020 0x00000002 ; Enabled the Delta-Sigma modulator. mem and 0x80680038 0xFFFFFFC0 mem or 0x80680038 0x00000001 ; Programmed Reference clock pre-divider in output clock divider register. mem and 0x80680030 0xFFFFF000 mem or 0x80680030 0x00000068 ; Programmed the integer feedback divider value in Freq Control 0 register. mem and 0x80680034 0xFF000000 mem or 0x80680034 0x002AAAAB ; Programmed the fractional feedback divider in Freq Control 0 register. mem and 0x80680020 0xFFFFFFDF ; Disabled the 4-phase clock generator (clk_4ph_en) in the control register. mem and 0x80680020 0xFFFFFFEF mem or 0x80680020 0x00000010 ; Enabled the FOUT4PHASE clocks in the control register. mem and 0x80680038 0xFFF8FFFF mem or 0x80680038 0x00020000 ; Set the first post-divider value (POSTDIV1) in the output divider control register. mem and 0x80680038 0xF8FFFFFF mem or 0x80680038 0x01000000 ; Set the second post-divider value (POSTDIV2) in the output divider control register. ; Programming HSDIV #0" mem read 0x80680080 mem and 0x80680080 0x7FFFFFFF mem or 0x80680080 0x80000000 mem and 0x80680080 0xFFFFFF80 mem or 0x80680080 0x00000003 mem and 0x80680080 0xFFFF7FFF mem or 0x80680080 0x00008000 mem and 0x80680080 0x7FFFFFFF mem read 0x80680080 ; HSDIV #0 programmed. ; Programming HSDIV #1 mem and 0x80680084 0x7FFFFFFF mem or 0x80680084 0x80000000 mem and 0x80680084 0xFFFFFF80 mem or 0x80680084 0x00000007 mem and 0x80680084 0xFFFF7FFF mem or 0x80680084 0x00008000 mem and 0x80680084 0x7FFFFFFF ; HSDIV #1 programmed. ; Programming HSDIV #2 mem and 0x80680088 0x7FFFFFFF mem or 0x80680088 0x80000000 mem and 0x80680088 0xFFFFFF80 mem or 0x80680088 0x00000009 mem and 0x80680088 0xFFFF7FFF mem or 0x80680088 0x00008000 mem and 0x80680088 0x7FFFFFFF ; HSDIV #2 programmed. ; Programming HSDIV #3 mem and 0x8068008C 0x7FFFFFFF mem or 0x8068008C 0x80000000 mem and 0x8068008C 0xFFFFFF80 mem or 0x8068008C 0x0000000E mem and 0x8068008C 0xFFFF7FFF mem or 0x8068008C 0x00008000 mem and 0x8068008C 0x7FFFFFFF ; HSDIV #3 programmed. ; Selected Main Domain PLL Controller. mem and 0x80410100 0xFFFFFFFE ;Cleared bit 0 in the PLL controller control register. mem and 0x80410100 0xFFFFFFDF ;Cleared bit 5 in the PLL Controller control register. ;PLL controller is now in bypass mode. ; Read the control register. mem read 0x80410000 ; returns 0x44815C00 mem and 0x8041012C 0xFFFFFF00 ; Set PLLDIV1 (output_div1). mem write 0x80410124 0x00008000 mem and 0x80410138 0xFFFFFFFE ;Clear GO; Set. mem read 0x8041013C ; returns 0x00000006 wait 10 ; GOSTAT is clear. mem and 0x80410118 0xFFFFFF00 mem or 0x80410118 0x00000001 ; Set PLLDIV1 (output_div1). mem and 0x80410140 0xFFFFFFFE ; Set ALN1." mem write 0x80410104 0x00000012 ; Set OCSEL to 0x12, point C on the observation clock input tree inside the PLL Controller. mem write 0x80410148 0x00000002 ; Set the clock control register to enable the OBSCLK output (bit 1). mem and 0x80410138 0xFFFFFFFE mem or 0x80410138 0x00000001 ; Set GO; Set to 1. mem read 0x8041013C ; returns 0x00000006 wait 10 ; GOSTAT is clear. ; Enable PLL Controller (write to bit 0 in control register)." mem write 0x80410100 0x00000049 mem and 0x80410138 0xFFFFFFFE ; Set GO; Set to 0. mem and 0x80410100 0xFFFFFFF7 ; PLLCTRL re; Set is cleared. PLLCTRL is free. mem and 0x80680020 0xFFFF7FFF mem or 0x80680020 0x00008000 ; Set the enable bit in the control register. mem read 0x80680024 ; returns 0x00000001 wait 10 ; PLL is locked. mem and 0x80680020 0x7FFFFFFF ; External bypass is disabled '0'. PLL and HSDIV clocks are engaging the rest of the SoC. ; Main PLL 0 (Main PLL) ; Set. ; Programming Main PLL 8 (ARM0 PLL) mem write 0x80688010 0x68EF3490 mem write 0x80688014 0xD172BC5A mem read 0x80688008 ; returns 0x00010801 mem and 0x80688020 0x7FFFFFFF mem or 0x80688020 0x80000000 mem and 0x80688020 0xFFFF7FFF mem or 0x80688020 0x00000000 mem and 0x80688020 0xFFFFFFFE mem or 0x80688020 0x00000001 mem and 0x80688020 0xFFFFFFFD mem or 0x80688020 0x00000002 mem and 0x80688038 0xFFFFFFC0 mem or 0x80688038 0x00000001 mem and 0x80688030 0xFFFFF000 mem or 0x80688030 0x00000068 mem and 0x80688034 0xFF000000 mem or 0x80688034 0x002AAAAB mem and 0x80688020 0xFFFFFFDF mem or 0x80688020 0x00000000 mem and 0x80688020 0xFFFFFFEF mem or 0x80688020 0x00000010 mem and 0x80688038 0xFFF8FFFF mem or 0x80688038 0x00010000 mem and 0x80688038 0xF8FFFFFF mem or 0x80688038 0x01000000 mem and 0x80688080 0x7FFFFFFF mem or 0x80688080 0x80000000 mem and 0x80688080 0xFFFFFF80 mem or 0x80688080 0x00000000 mem and 0x80688080 0xFFFF7FFF mem or 0x80688080 0x00008000 mem and 0x80688080 0x7FFFFFFF mem or 0x80688080 0x00000000 mem and 0x80688020 0xFFFF7FFF mem or 0x80688020 0x00008000 mem read 0x80688024 ; returns 0x00000001 wait 10 mem and 0x80688020 0x7FFFFFFF mem or 0x80688020 0x00000000 echo PLL init done. ; Powering up LPSC_A72_CLUSTER_0 mem write 0x80400338 0x00000001 mem write 0x80400B38 0x00000103 mem write 0x80400120 0x00004000 wait 100 ; Powering up LPSC_A72_CLUSTER_0_PBIST mem write 0x80400338 0x00000001 mem write 0x80400B3C 0x00000103 mem write 0x80400120 0x00004000 wait 100 ; Powering up LPSC_A72_0 mem write 0x8040033C 0x00000001 mem write 0x80400B40 0x00000103 mem write 0x80400120 0x00008000 wait 100 ; Powering up LPSC_A72_1 mem write 0x80400340 0x00000001 mem write 0x80400B44 0x00000103 mem write 0x80400120 0x00010000 wait 100 echo Run J7200 firmware ; load ti-fs-firmware-j7200-gp.bin mem load "card:sysfw.bin", BIN, 0x40000 gm 0x40000 wait 200 [INIT_R5.tcl] mon {clock 10000} # check if PINMUX is already initialized set addr 0x4301c0c0 mon "memory read $addr" set val [mrw $addr] if {!= $val 0x00050007} \ {mon {run $r5_init}} \ {puts "Skip R5 initialization"} [r5_init] ; load fls_peedi_mcu1_0_release.xer5f mem load "card:fls.elf" ELF go echo Please wait 8s till this message: echo "Cortex-R5 - stopped by breakpoint" [FLASH_SPI] CHIP = SPI25_FLASH CPU = TI_J7200 FILE = "test32k.bin" BIN 0x100000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] DEFAULT_CORE = 2 PROMPT = "dra821> " ; telnet prompt [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase 0 1024*1024*16 ; erase 16MB [prog] ; program flash flash prog bin/tiboot3.bin 0 flash prog bin/tispl.bin 0x100000 flash prog bin/u-boot.bin 0x300000 flash prog bin/vxWorks.bin 0x800000 [ver] flash verify bin/tiboot3.bin 0 flash verify bin/tispl.bin 0x100000 flash verify bin/u-boot.bin 0x300000 flash verify bin/vxWorks.bin 0x800000