;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Fujitsu MB86R12 ’Emerald-P’ ; Supported board : SK-86R12-01 ; ; Revision : 1.0 ; ; Date : August 23, 2012 ; ; Note: Set PSMODE dip switch (SW11-6) OFF ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2012, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp:; 192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp:; user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = CortexA8 ; platform is CortexA8 [PLATFORM_CortexA8] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 25000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 100 ; length of RESET pulse in ms; 0 means no RESET CORE0 = Cortex-A, 0, 0x1BA00477 ; TAP is MB86R12 CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_NOR ; init section only for NOR Flash ;CORE0_INIT = INIT_EMERALD ; full init section ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT CORE0_FLASH0 = NOR_FLASH ; FLASH section parameters CORE0_WORKSPACE = 0x100000, 0x8000 ; address, length in bytes ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp:; 192.168.1.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp:; 192.168.1.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp:; 192.168.3.1" ;CORE0_PATH = "card:; " CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_EMERALD] ; Release only CRG_P and DDR controller reset mem write 0x3B500028 0x00000081 ; CRRRS (Register controlled reset request register) ; Dsiable Watch dog timer to prevent System reset mem write 0x04a00000 0xEDACCE55 mem write 0x04a00048 0x01000000 ; Configure Global control register mem write 0x3d100100 0x00003F00 ; GLBLCTL(Global control) Register: All UARTs are in UART mode ; Additionally release CRG_P bus reset in CRG_S mem write 0x3B500028 0xC0000081 ; CRRRS (Register controlled reset request register) ; Clock speed down ; CRG_S mem write 0x3B500100 0x0000000F ; CRDM0 (Clock divider mode register) mem write 0x3B500110 0x0000000F ; CRDM1 (Clock divider mode register) mem write 0x3B500120 0x0000000F ; CRDM2 (Clock divider mode register) mem write 0x3B500130 0x0000000F ; CRDM3 (Clock divider mode register) mem write 0x3B500140 0x0000000F ; CRDM4 (Clock divider mode register) mem write 0x3B500150 0x0000000F ; CRDM5 (Clock divider mode register) mem write 0x3B500160 0x0000000F ; CRDM6 (Clock divider mode register) mem write 0x3B500170 0x0000000F ; CRDM7 (Clock divider mode register) mem write 0x3B500180 0x0000000F ; CRDM8 (Clock divider mode register) mem write 0x3B500190 0x0000000F ; CRDM9 (Clock divider mode register) mem write 0x3B5001A0 0x0000000F ; CRDMA (Clock divider mode register) mem write 0x3B5001B0 0x0000000F ; CRDMB (Clock divider mode register) mem write 0x3B5001C0 0x0000000F ; CRDMC (Clock divider mode register) mem write 0x3B5001D0 0x0000000F ; CRDMD (Clock divider mode register) mem write 0x3B5001E0 0x0000000F ; CRDME (Clock divider mode register) mem write 0x3B5001F0 0x0000000F ; CRDMF (Clock divider mode register) mem write 0x3B500030 0x00000001 ; CRCDC (Clock divider control register): DCHREQ (Clock divider mode update request) is set wait 50 ; Poll CRG_S.CRCDC.DCHREQ until changed to 0 ; CRG_P mem write 0x3E200100 0x0000000F ; CRDM0 (Clock divider mode register) mem write 0x3E200110 0x0000000F ; CRDM1 (Clock divider mode register) mem write 0x3E200120 0x0000000F ; CRDM2 (Clock divider mode register) mem write 0x3E200130 0x0000000F ; CRDM3 (Clock divider mode register) mem write 0x3E200140 0x0000000F ; CRDM4 (Clock divider mode register) mem write 0x3E200150 0x0000000F ; CRDM5 (Clock divider mode register) mem write 0x3E200160 0x0000000F ; CRDM6 (Clock divider mode register) mem write 0x3E200170 0x0000000F ; CRDM7 (Clock divider mode register) mem write 0x3E200180 0x0000000F ; CRDM8 (Clock divider mode register) mem write 0x3E200190 0x0000000F ; CRDM9 (Clock divider mode register) mem write 0x3E2001A0 0x0000000F ; CRDMA (Clock divider mode register) mem write 0x3E2001B0 0x0000000F ; CRDMB (Clock divider mode register) mem write 0x3E2001C0 0x0000000F ; CRDMC (Clock divider mode register) mem write 0x3E2001D0 0x0000000F ; CRDMD (Clock divider mode register) mem write 0x3E2001E0 0x0000000F ; CRDME (Clock divider mode register) mem write 0x3E2001F0 0x0000000F ; CRDMF (Clock divider mode register) mem write 0x3E200030 0x00000001 ; CRCDC (Clock divider control register): DCHREQ (Clock divider mode update request) is set wait 50 ; Poll CRG_P.CRCDC.DCHREQ until changed to 0 ; **************************************** ; Enable PLL bypass mode ; **************************************** ; CRG_S mem write 0x3B500000 0x010f003f ; CRPLC (PLL control register) ; CRG_P mem write 0x3E200000 0x010f003f ; CRPLC (PLL control register) ; **************************************** ; Confiugre PLL lock up wait time and stop PLL ; **************************************** ; CRG_S mem write 0x3B500000 0x010f0000 ; CRPLC (PLL control register) ; CRG_P mem write 0x3E200000 0x010f0000 ; CRPLC (PLL control register) ; ------------------------------------- ; 533 Mhz ; Note: - Set PSMODE dip switch (SW11-6) OFF ; - Adapte DDR memory init ; ------------------------------------- mem write 0x3D100600 0x00001043 ; SSCGCTL: CLKSEL=PLL,DISPCLK=PLL, IDIV= 32 ; **************************************** ; Activate PLL ; **************************************** ; CRG_S mem write 0x3B500000 0x010f003F ; CRPLC (PLL control register) ; CRG_P mem write 0x3E200000 0x010f003F ; CRPLC (PLL control register) ; **************************************** ; Poll CRG_x.CRRDY.PLLRD until changed to 1 ; **************************************** wait 50 ; wait PLLRDY ; **************************************** ; Disable PLL bypass mode ; **************************************** ; CRG_S mem write 0x3B500000 0x000f003f ; CRPLC (PLL control register) ; CRG_P mem write 0x3E200000 0x000f003f ; CRPLC (PLL control register) ; **************************************** ; Clock speed up ; **************************************** ; CRG_S mem write 0x3B500100 0x00000000 ; CRDM0 (Clock divider mode register): 1/1 ARM clock (533Mhz) mem write 0x3B500110 0x00000001 ; CRDM1 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3B500120 0x00000001 ; CRDM2 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3B500130 0x00000003 ; CRDM3 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B500140 0x00000003 ; CRDM4 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B500150 0x00000003 ; CRDM5 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B500160 0x00000003 ; CRDM6 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B500170 0x00000003 ; CRDM7 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B500180 0x00000001 ; CRDM8 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3B500190 0x00000007 ; CRDM9 (Clock divider mode register): 1/8 APB clock (66Mhz) mem write 0x3B5001A0 0x00000003 ; CRDMA (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B5001B0 0x0000000B ; CRDMB (Clock divider mode register): 1/12 SDI clock (44.3Mhz) mem write 0x3B5001C0 0x00000003 ; CRDMC (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3B5001D0 0x00000009 ; CRDMD (Clock divider mode register): 1/10 TS clock (53.3Mhz) mem write 0x3B5001E0 0x00000001 ; CRDME (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3B5001F0 0x00000007 ; CRDMF (Clock divider mode register): 1/8 APB clock (66Mhz) mem write 0x3B500030 0x00000001 ; CRCDC (Clock divider control register): DCHREQ (Clock divider mode update request) is set wait 50 ; Poll CRG_S.CRCDC.DCHREQ until changed to 0 ; CRG_P mem write 0x3E200100 0x00000000 ; CRDM0 (Clock divider mode register): 1/1 ARM clock (533Mhz) mem write 0x3E200110 0x00000001 ; CRDM1 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3E200120 0x00000001 ; CRDM2 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3E200130 0x00000003 ; CRDM3 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E200140 0x00000003 ; CRDM4 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E200150 0x00000003 ; CRDM5 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E200160 0x00000003 ; CRDM6 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E200170 0x00000003 ; CRDM7 (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E200180 0x00000001 ; CRDM8 (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3E200190 0x00000007 ; CRDM9 (Clock divider mode register): 1/8 APB clock (66Mhz) mem write 0x3E2001A0 0x00000003 ; CRDMA (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E2001B0 0x0000000B ; CRDMB (Clock divider mode register): 1/12 SDI clock (44.3Mhz) mem write 0x3E2001C0 0x00000003 ; CRDMC (Clock divider mode register): 1/4 AHB clock (133Mhz) mem write 0x3E2001D0 0x00000009 ; CRDMD (Clock divider mode register): 1/10 TS clock (53.3Mhz) mem write 0x3E2001E0 0x00000001 ; CRDME (Clock divider mode register): 1/2 AXI clock (266Mhz) mem write 0x3E2001F0 0x00000007 ; CRDMF (Clock divider mode register): 1/8 APB clock (66Mhz) mem write 0x3E200030 0x00000001 ; CRCDC (Clock divider control register): DCHREQ (Clock divider mode update request) is set wait 50 ; Poll CRG_P.CRCDC.DCHREQ until changed to 0 ; **************************************** ; Enable other modules ; **************************************** mem write 0x3B500028 0xE7FF7FFF ; CRRRS (Register controlled reset request register): Deasserting request for RRESET: Watchdog is not released ; **************************************** ; Configure external bus interface ; **************************************** ; CS0: NOR flash mem write 0x3C400000 0x00000021 ; Mode0 mem write 0x3C400020 0x05282F03 ; Tim0 -> E3 eva mem write 0x3C400040 0x007f0000 ; Area0 -> 128MB ; CS2: External Ethernet mem write 0x3C400008 0x00000001 ; Mode2 ; mem write 0x3C400028 0x050E000E ; Tim2 mem write 0x3C400048 0x000000F0 ; Area2 ; Internal CS mem write 0x3C40000C 0x00000001 ; Mode3 mem write 0x3C400010 0x00000001 ; Mode4 mem write 0x3C400014 0x00000001 ; Mode5 mem write 0x3C400018 0x00000001 ; Mode6 mem write 0x3C40001C 0x00000001 ; Mode6 mem write 0x3C40002C 0x055FF00F ; Tim3 mem write 0x3C400030 0x055FF00F ; Tim4 mem write 0x3C400034 0x055FF00F ; Tim5 mem write 0x3C400038 0x055FF00F ; Tim6 mem write 0x3C40003C 0x055FF00F ; Tim7 mem write 0x3C40004C 0x00000080 ; Area3 mem write 0x3C400050 0x00000080 ; Area4 mem write 0x3C400054 0x00000080 ; Area5 mem write 0x3C400058 0x00000080 ; Area6 mem write 0x3C40005C 0x00000080 ; Area7 ; **************************************** ; Initalize DDR memory ; **************************************** mem write 0x38400400 0x00000000 ; REG_STR mem write 0x38400404 0x001F0000 ; REG_MCC mem write 0x38400408 0x00000000 ; REG_RST mem write 0x3840040C 0x00000000 ; REG_PWR0 mem write 0x38400410 0x00000000 ; REG_PWR1 mem write 0x38400414 0x00000000 ; REG_INIT0 mem write 0x38400418 0x00000000 ; REG_INIT1 mem write 0x3840041C 0x00FF0F01 ; REG_INIT2 ; r_cdrv_ck = r_cdrv_cmd = = r_cdrv_dq0 = r_cdrv_dq1 = r_cdrv_dq2 = r_cdrv_dq3 = 11b [34 ohm], mem write 0x38400420 0x01C92222 ; REG_INIT3 ; r_rte = 01b SOC side ODT impedance 120ohm mem write 0x38400424 0x08080808 ; REG_INIT4 mem write 0x38400428 0x0000AA00 ; REG_INIT5 mem write 0x3840042C 0x000F2108 ; REG_TDS0 ; r_rxdqs_sft_0 = 15 (0Fh), r_txdq_sft_0 = 33 (21h) mem write 0x38400430 0x000F2108 ; REG_TDS1 ; r_rxdqs_sft_1 = 15 (0Fh), r_txdq_sft_1 = 33 (21h) mem write 0x38400434 0x000F2808 ; REG_TDS2 ; r_rxdqs_sft_2 = 15 (0Fh), r_txdq_sft_2 = 40 (28h) mem write 0x38400438 0x000F2708 ; REG_TDS3 ; r_rxdqs_sft_3 = 15 (0Fh), r_txdq_sft_3 = 39 (27h) ; ---------------------------------------- ; MCR_0-MCR92 configuration for DDR3-1066F CL=7 2Gbit : MT41J128M16HA-15E ; ---------------------------------------- mem write 0x38400000 0x00000600 ; MCR_0 mem write 0x38400004 0x00000000 ; MCR_1 mem write 0x38400008 0x00000006 ; MCR_2 mem write 0x3840000C 0x0001A0AB ; MCR_3 mem write 0x38400010 0x000411AB ; MCR_4 mem write 0x38400014 0x06000E00 ; MCR_5 mem write 0x38400018 0x1B040404 ; MCR_6 mem write 0x3840001C 0x04070414 ; MCR_7 mem write 0x38400020 0x91DD0C04 ; MCR_8 mem write 0x38400024 0x00040300 ; MCR_9 mem write 0x38400028 0x08070001 ; MCR_10 mem write 0x3840002C 0x0002000F ; MCR_11 mem write 0x38400030 0x00001B03 ; MCR_12 mem write 0x38400034 0x00000007 ; MCR_13 mem write 0x38400038 0x00005601 ; MCR_14 mem write 0x3840003C 0x00001033 ; MCR_15 mem write 0x38400040 0x000D0004 ; MCR_16 mem write 0x38400044 0x005B0200 ; MCR_17 mem write 0x38400048 0x00010000 ; MCR_18 mem write 0x3840004C 0x00083000 ; MCR_19 mem write 0x38400050 0x00880042 ; MCR_20 ; mr1_data_0 is modified => M9,M6,M2 = 0,1,0: RZQ/2 (120 ohm [NOM]) mem write 0x38400054 0x02000000 ; MCR_21 mem write 0x38400058 0x00000100 ; MCR_22 mem write 0x3840005C 0x02400040 ; MCR_23 mem write 0x38400060 0x01030100 ; MCR_24 mem write 0x38400064 0x01FFFF0A ; MCR_25 mem write 0x38400068 0x01010101 ; MCR_26 mem write 0x3840006C 0x000C0001 ; MCR_27 mem write 0x38400070 0x00000000 ; MCR_28 mem write 0x38400074 0x00000001 ; MCR_29 mem write 0x38400078 0x00000000 ; MCR_30 mem write 0x3840007C 0x00000000 ; MCR_31 mem write 0x38400080 0x00000000 ; MCR_32 mem write 0x38400084 0x00000000 ; MCR_33 mem write 0x38400088 0x00000000 ; MCR_34 mem write 0x3840008C 0x00000000 ; MCR_35 mem write 0x38400090 0x00000000 ; MCR_36 mem write 0x38400094 0x02000002 ; MCR_37 mem write 0x38400098 0x00000000 ; MCR_38 mem write 0x3840009C 0x00000000 ; MCR_39 mem write 0x384000A0 0x00000000 ; MCR_40 mem write 0x384000A4 0x00000000 ; MCR_41 mem write 0x384000A8 0x00002819 ; MCR_42 mem write 0x384000AC 0x00000000 ; MCR_43 mem write 0x384000B0 0x00001000 ; MCR_44 wrlvl_delay_0 = 16 (10h) mem write 0x384000B4 0x00170010 ; MCR_45 wrlvl_delay_2 = 23 (17h), wrlvl_delay_1 = 16 (10h) mem write 0x384000B8 0x00000016 ; MCR_46 wrlvl_delay_3 = 22 (16h) mem write 0x384000BC 0x00000000 ; MCR_47 mem write 0x384000C0 0x00000000 ; MCR_48 mem write 0x384000C4 0x00000000 ; MCR_49 mem write 0x384000C8 0x00000000 ; MCR_50 mem write 0x384000CC 0x00290000 ; MCR_51 rdlvl_gate_delay_0 = 41 (29h) mem write 0x384000D0 0x00000000 ; MCR_52 mem write 0x384000D4 0x00000000 ; MCR_53 mem write 0x384000D8 0x00000000 ; MCR_54 mem write 0x384000DC 0x00000028 ; MCR_55 rdlvl_gate_delay_1 = 40 (28h) mem write 0x384000E0 0x00000000 ; MCR_56 mem write 0x384000E4 0x00000000 ; MCR_57 mem write 0x384000E8 0x00300000 ; MCR_58 rdlvl_gate_delay_2 = 48 (30h) mem write 0x384000EC 0x00000000 ; MCR_59 mem write 0x384000F0 0x00000000 ; MCR_60 mem write 0x384000F4 0x00000000 ; MCR_61 mem write 0x384000F8 0xFFFF002F ; MCR_62 rdlvl_gate_delay_3 = 47 (2Fh) mem write 0x384000FC 0x00000101 ; MCR_63 configure priority mem write 0x38400100 0x0101FFFF ; MCR_64 configure priority mem write 0x38400104 0x02FFFF00 ; MCR_65 mem write 0x38400108 0xFFFF0002 ; MCR_66 mem write 0x3840010C 0x00000202 ; MCR_67 mem write 0x38400110 0x0101FFFF ; MCR_68 configure priority mem write 0x38400114 0x00000000 ; MCR_69 mem write 0x38400118 0x01010101 ; MCR_70 mem write 0x3840011C 0x01003200 ; MCR_71 mem write 0x38400120 0x01010101 ; MCR_72 mem write 0x38400124 0x01010032 ; MCR_73 mem write 0x38400128 0x00020101 ; MCR_74 mem write 0x3840012C 0x01010032 ; MCR_75 mem write 0x38400130 0x00030101 ; MCR_76 mem write 0x38400134 0x01010032 ; MCR_77 mem write 0x38400138 0x00040101 ; MCR_78 mem write 0x3840013C 0x00000032 ; MCR_79 mem write 0x38400140 0x00000000 ; MCR_80 mem write 0x38400144 0x02000A02 ; MCR_81 mem write 0x38400148 0x10330000 ; MCR_82 mem write 0x3840014C 0x00000000 ; MCR_83 mem write 0x38400150 0x00000000 ; MCR_84 mem write 0x38400154 0x06050000 ; MCR_85 mem write 0x38400158 0x060F0000 ; MCR_86 mem write 0x3840015C 0x001A1401 ; MCR_87 mem write 0x38400160 0x00000000 ; MCR_88 mem write 0x38400164 0x00000000 ; MCR_89 mem write 0x38400168 0x00000000 ; MCR_90 mem write 0x3840016C 0x1101020F ; MCR_91 mem write 0x38400170 0x00000013 ; MCR_92 ; ---------------------------------------- ; Reset sequence ; ---------------------------------------- ; 60ns or more wait wait 1 mem write 0x38400408 0x0000000F ; REG_RST: release rx_rstx_ck|rx_rstx_cmd|rx_rstx_dqdqs|rx_rstx_pzq| ; 120ns or more wait wait 1 mem write 0x38400408 0x0003000F ; REG_RST: release rx_dllrstx|rx_pzqrstx ; tDLL_LOCK[ns] + 40 ns or more wait wait 1 mem write 0x38400408 0x0007000F ; REG_RST: release rx_softrstx ; ---------------------------------------- ; PZQ initial calibration ; ---------------------------------------- ; tPZQ_INIT or more wait wait 1 mem write 0x38400440 0x00000000 ; REG_UP: update can do the PZQ initial calibration wait 1 mem write 0x38400404 0x001F0001 ; REG_MCC: AXI port Y coherent bufferable selection ; 100ns or more wait wait 1 ; 50 ns or more wait wait 1 ; ---------------------------------------- ; Initialization of SDRAM ; ---------------------------------------- mem write 0x38400000 0x00000601 ; MCR0: DRAM_CLASS= | Initiate cmd processing in the controller -> set DDR3 wait 1 ; The initialization is completed when the INT_STATUS 5 bit of MCR_29 register is set ; Additionally, the interrupt signal o_DDR3C_INT=1 is output. ; pause 1 ; INT_STATUS 5 bit is cleared to "0" by writing "1" in the INT_ACK 5 bit of MCR_30 register after ; initialization is completed. At the same time, the interrupt signal o_DDR3C_INT is set ; pause 1 ; ---------------------------------------- ; Select DDR slave interface ; ---------------------------------------- mem write 0x3b200060 0x0 ; DSX0SEL (Default Slave AXI_0 register): Select Slave I/F wait 1 ; **************************************** ; Enable multiplexed I/O ; **************************************** mem write 0x3D100200 0x82000000 ; PINMUX (Pin Multiplex): Pinmux is enabled; PinmuxB-PinmuxI = Mode0 ; only needed for U-boot clock setup mem write 0x00104000 0x03F948CE ; sys_clk = 66.66875MHz mem write 0x00104010 0x03F948CE ; sys_ns16550_clk = 66.66875MHz ; mem write 0x00104000 0x2FAF080 ; sys_clk = 50MHz ; mem write 0x00104010 0x2FAF080 ; sys_ns16550_clk = 50MHz [INIT_NOR] ; CS0: NOR flash mem write 0x3C400000 0x00000021 ; Mode0 mem write 0x3C400020 0x05282F03 ; Tim0 -> E3 eva mem write 0x3C400040 0x007f0000 ; Area0 -> 128MB ; Enable multiplexed I/O mem write 0x3D100200 0x82000000 ; PINMUX (Pin Multiplex): Pinmux is enabled; PinmuxB-PinmuxI = Mode0 [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 10000 stop break del all [NOR_FLASH] CHIP = CFI_FLASH BASE_ADDR = 0xE0000000 ACCESS_METHOD = AGENT FILE = myfile.bin, 0xE0000000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "emerald> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog