;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : i.MX51 ; Supported board : Digi i.MX51 Development Board ; ; Revision : 1.2 ; ; Date : May 12, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is Cortex-A [PLATFORM_Cortex-A] JTAG_CHAIN = 5, 4, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 16000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 50 CORE0 = Cortex-A, 2, 0x1BA00477 ; TAP is i.MX51 CPU CORE0_DEBUG_ADDR = 0xE0008000 ; note: i.MX51 doesn't have ROM table CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_BOARD ; init section with booting Linux ;CORE0_INIT = INIT_LINUX ; init section with booting Linux CORE0_WORKSPACE = 0x1FFE0000, 0x20000 ; SRAM ;CORE0_WORKSPACE = 0xA0000000, 0x10000 ; DDR2 CORE0_FLASH = FLASH_NAND ; NAND FLASH parameters ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 20000 stop break del all beep 100 100 [INIT_BOARD] ;Target Setup: initialize DRAM controller and peripherals for CCWMX51 echo "Configuring CCWMX51..." set control 0x00050078 ; Set supervisor mode set cpsr 0x1D3 ; Setup PLL's mem wr 0x83F80004 0x00000000 mem wr 0x83F84004 0x00000000 mem wr 0x83F88004 0x00000000 ; PLL1 @800MHz, assumed 25MHz crystal mem wr 0x83F80000 0x00001232 mem wr 0x83F80008 0x00000080 mem wr 0x83F8000C 0x0 mem wr 0x83F80010 0x0 ; PLL3 @400MHz, assumed 25MHz crystal mem wr 0x83F88000 0x00001232 mem wr 0x83F88008 0x00000040 mem wr 0x83F8800C 0x00000001 mem wr 0x83F88010 0x00000000 ; Switch ARM to PLL 3 mem wr 0x73FD400C 0x00000180 mem wr 0x73FD400C 0x00000184 mem wr 0x83F80000 0x00001232 wait 500 ; Switch ARM back to PLL 1 mem wr 0x73FD400C 0x00000180 mem wr 0x73FD400C 0x00000000 ; Restart PLL3 mem wr 0x83F88000 0x00000232 wait 50 clock normal ; remove this when INIT used for multicore mem wr 0x83F80004 0x00000002 mem wr 0x83F88004 0x00000002 ;============================ ; Disable WDOG ;============================ echo "Disabling Watchdog..." mem wr16 0x73f98000 0x30 ;============================ ; Initialization script for 32 bit DDR ;============================ echo "Setting DDR..." ; Set CCM registers mem wr 0x73fd4014 0x19239100 mem wr 0x73fd4018 0x000020C2 mem wr 0x73fd401C 0xA5A2A020 mem wr 0x73fd4024 0x00C30321 mem wr 0x73fd4060 0x010900F0 mem wr 0x73fa83F4 0x00000004 mem wr 0x73fa83F0 0x00000004 ;============================ ;Initialization script for 32 bit DDR2 (CS0+CS1) ;Starting DDR frequency (after ROM code execution, before "prog_pll") ;is 150MHz. ;Using validation environment (incl. "prog_pll" routine) ;will set DDR clock to 200MHz. ;============================ ;DDR2 IOMUX configuration mem wr 0x73fa88a0 0x00000200 ;IOMUXC_SW_PAD_CTL_GRP_INMODE1 DDR2 mode mem wr 0x73fa850c 0x000020c5 ;IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT1 Pull-D, HIGH DS mem wr 0x73fa8510 0x000020c5 ;IOMUXC_SW_PAD_CTL_PAD_EIM_SDODT0 Pull-D, HIGH DS mem wr 0x73fa883c 0x00000002 ;IOMUXC_SW_PAD_CTL_GRP_DDR_A0 MEDIUM DS mem wr 0x73fa8848 0x00000002 ;IOMUXC_SW_PAD_CTL_GRP_DDR_A1 MEDIUM DS mem wr 0x73fa84b8 0x000000e7 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS mem wr 0x73fa84bc 0x00000045 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 Pull/Keep Disable mem wr 0x73fa84c0 0x00000045 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 Pull/Keep Disable mem wr 0x73fa84c4 0x00000045 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 Pull/Keep Disable mem wr 0x73fa84c8 0x00000045 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 Pull/Keep Disable mem wr 0x73fa8820 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKS PUE = Keeper mem wr 0x73fa84a4 0x00000003 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS MEDIUM DS mem wr 0x73fa84a8 0x00000003 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS MEDIUM DS mem wr 0x73fa84ac 0x000000e3 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE MEDIUM DS mem wr 0x73fa84b0 0x000000e3 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 MEDIUM DS mem wr 0x73fa84b4 0x000000e3 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 MEDIUM DS mem wr 0x73fa84cc 0x000000e3 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0 MEDIUM DS mem wr 0x73fa84d0 0x000000e2 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1 MEDIUM DS mem wr 0x73FA882C 0x4 ; DRAM_D31-24 to high mem wr 0x73FA88a4 0x4 ; DRAM_D0-7 to high mem wr 0x73FA88aC 0x4 ; DRAM_D8-15 to high mem wr 0x73FA88b8 0x4 ; DRAM_D16-23 to high ;13 ROW, 10 COL, 32Bit, SREF=4 Micron Model, CAS=3, BL=4 mem wr 0x83fd9000 0x82a20000 ; ESDCTL0 mem wr 0x83fd9008 0x82a20000 ; ESDCTL1 mem wr 0x83fd9010 0x000ad0d0 ; ESDMISC ;ESDCFG0 tRFC=13 tXSR=28 tXP=2 tRP=3 tMRD=2 tRAS=8 tRRD=2 tWR=3 tRCD=3 tRC=11 mem wr 0x83fd9004 0x3f3584ab ;0x333574aa ;ESDCFG1 tRFC=13 tXSR=28 tXP=2 tRP=3 tMRD=2 tRAS=8 tRRD=2 tWR=3 tRCD=3 tRC=11 mem wr 0x83fd900c 0x3f3584ab ;0x333574aa ;Init DRAM on CS0 mem wr 0x83fd9014 0x04008008 ; ESDSCR mem wr 0x83fd9014 0x0000801a ; ESDSCR mem wr 0x83fd9014 0x0000801b ; ESDSCR mem wr 0x83fd9014 0x00448019 ; ESDSCR mem wr 0x83fd9014 0x07328018 ; ESDSCR mem wr 0x83fd9014 0x04008008 ; ESDSCR mem wr 0x83fd9014 0x00008010 ; ESDSCR mem wr 0x83fd9014 0x00008010 ; ESDSCR mem wr 0x83fd9014 0x06328018 ; ESDSCR mem wr 0x83fd9014 0x03808019 ; ESDSCR mem wr 0x83fd9014 0x00408019 ; ESDSCR ODT=150Ohm,CS0 mem wr 0x83fd9014 0x00008000 ; ESDSCR ;Init DRAM on CS1 mem wr 0x83fd9014 0x0400800c ; ESDSCR mem wr 0x83fd9014 0x0000801e ; ESDSCR mem wr 0x83fd9014 0x0000801f ; ESDSCR mem wr 0x83fd9014 0x0000801d ; ESDSCR mem wr 0x83fd9014 0x0732801c ; ESDSCR mem wr 0x83fd9014 0x0400800c ; ESDSCR mem wr 0x83fd9014 0x00008014 ; ESDSCR mem wr 0x83fd9014 0x00008014 ; ESDSCR mem wr 0x83fd9014 0x0632801c ; ESDSCR mem wr 0x83fd9014 0x0380801d ; ESDSCR mem wr 0x83fd9014 0x0040801d ; ESDSCR ODT=150Ohm,CS0 mem wr 0x83fd9014 0x00008004 ; ESDSCR mem wr 0x83fd9000 0xb2a20000 ; ESDCTL0 mem wr 0x83fd9008 0xb2a20000 ; ESDCTL1 mem wr 0x83fd9010 0x000ad6d0 ; ESDMISC RALAT=01, NO ODT mem wr 0x83fd9034 0x90000000 ; ESDCDLYGD mem wr 0x83fd9014 0x00000000 ; ESDSCR - clear "configuration request" bit echo "Initialisation completed..." [FLASH_NAND] CHIP = NAND_FLASH CPU = iMX51 ADDR_BASE = 0 FILE = "u-boot.bin", 0x00000000 ;BAD_BLOCKS = 2819, 3067, 3071, 3585 ERASE_BAD_BLOCKS= NO OOB_INFO = IMX_ECC [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "imx51> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog