;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : i.MX53 ; Supported board : Digi i.MX53 Development Board ; ; Revision : 1.1 ; ; Date : April 24, 2013 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is Cortex-A [PLATFORM_Cortex-A] JTAG_CHAIN = 5, 4, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 100, 5000 ;JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 50 CORE0 = Cortex-A, 2, 0x1BA00477 CORE0_DEBUG_ADDR = 0xC0008000 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_BOARD ; init section to program NAND ;CORE0_INIT = INIT_LINUX ; init section to debug Linux kernel CORE0_WORKSPACE = 0x70000000, 0x10000 ; CSD0 DDR CORE0_FLASH = FLASH_NAND ; NAND FLASH parameters [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 20000 stop break del all beep 100 100 [INIT_BOARD] ;Target Setup: initialize DRAM controller and peripherals for CCWi-i.MX53 echo "Configuring CCWi-i.MX53..." ; ================================================================================================ ; Disable WDOG ; ================================================================================================ echo "Disabling Watchdog..." mem wr16 0x53f98000 0x30 ; ================================================================================================ ; Enable all clocks (they are disabled by ROM code) ; ================================================================================================ mem wr 0x53FD4068 0xFFFFFFFF mem wr 0x53FD406C 0xFFFFFFFF mem wr 0x53FD4070 0xFFFFFFFF mem wr 0x53FD4074 0xFFFFFFFF mem wr 0x53FD4078 0xFFFFFFFF mem wr 0x53FD407C 0xFFFFFFFF mem wr 0x53FD4080 0xFFFFFFFF mem wr 0x53FD4084 0xFFFFFFFF ; ====================================== ; Initialization script for 32 bit DDR2 ; ====================================== echo "Setting DDR2..." ; ====================================== ; DDR2 IOMUX configuration ; ====================================== mem wr 0x53fa8554 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 mem wr 0x53fa8558 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 mem wr 0x53fa8560 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 mem wr 0x53fa8564 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 mem wr 0x53fa8568 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 mem wr 0x53fa8570 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 mem wr 0x53fa8574 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS mem wr 0x53fa8578 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 mem wr 0x53fa857c 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 mem wr 0x53fa8580 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 mem wr 0x53fa8584 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 mem wr 0x53fa8588 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS mem wr 0x53fa8590 0x00380040 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 mem wr 0x53fa8594 0x00380000 ;IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 mem wr 0x53fa86f0 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_ADDDS mem wr 0x53fa86f4 0x00000200 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL mem wr 0x53fa86fc 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRPKE mem wr 0x53fa8714 0x00000000 ;IOMUXC_SW_PAD_CTL_GRP_DDRMODE - CMOS mode mem wr 0x53fa8718 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_B0DS mem wr 0x53fa871c 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_B1DS mem wr 0x53fa8720 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_CTLDS mem wr 0x53fa8724 0x02000000 ;IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL0= mem wr 0x53fa8728 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_B2DS mem wr 0x53fa872c 0x00380000 ;IOMUXC_SW_PAD_CTL_GRP_B3DS ; ====================================== ; Initialize DDR2 memory ; ====================================== mem wr 0x63fd9088 0x2d313331 ;ESDCTL.RDDLCTL mem wr 0x63fd9090 0x393b3836 ;ESDCTL.WRDLCTL mem wr 0x63fd90F8 0x00000800 ;ESDCTL.MUR mem wr 0x63fd907c 0x020c0211 ;ESDCTL.DGCTRL0 mem wr 0x63fd9080 0x014c0155 ;ESDCTL.DGCTRL1 ; ESDCTL Miscellaneous Register ; ONE_CS = 0b0 -- Two chip select are used, 1 GB per chip select. ; BI_ON = 0b1 -- Banks are interleaved, and address is decoded as row-bank-column ; MIF3_MODE = 0b11 ; RALAT = 0b011 -- 3 cycles additional latency ; DDR_4_BANK = 0b0 -- 8 banks device is being used ; DDR_TYPE = 0b10 -- DDR2 device is used. (Default) mem wr 0x63fd9018 0x000016d0 ;ESDMISC ; ESDCTL Control Register ; SDE_0 = 0b1 -- Enhanced SDRAM Controller Enabled ; SDE_1 = 0b1 -- Enhanced SDRAM Controller Enabled ; ROW = 0b100 -- Row Address Width. 15 bits Row ; COL = 0b001 -- Column Address Width. 10 bits Column ; BL = 0b0 -- Burst Length = 4 ; DSIZ = 0b1 -- SDRAM Memory Data Width = 32-bit memory width mem wr 0x63fd9000 0xc4110000 ;ESDCTL ; ESDCTL Timing Configuration Register 0 ; tRFC = 0x4D -- REF command to ACT. ; tXS = 0x51 -- Exit self refresh to non READ command ; tXP = 0x1 -- Exit precharge power down to any command ; tXPDLL = 0x1 -- Exit active power down to read commands ; tFAW = 0xD -- Four Active Window (all banks). ; tCL = 0x2 -- CAS Read Latency mem wr 0x63fd900C 0x4d5122d2 ;ESDCTL.ESDCFG0 ; ESDCTL Timing Configuration Register 1 ; tRCD = 0x4 -- ACT command to internal read or write delay time ; tRP = 0x4 -- PRE command period ; tRC = 0x16 -- ACT to ACT or REF command period ; tRAS = 0x11 -- ACT to PRE command period ; tRPA = 0x1 -- Precharge-all command period ; tWR = 0x5 -- WRITE recovery time ; tMRD = 0x1 -- Mode Register Set command cycle ; tCWL = 0x2 -- CAS Write Latency mem wr 0x63fd9010 0x92d18a22 ;ESDCTL.ESDCFG1 ; ESDCTL Timing Configuration Register 2 ; tDLLK/tXSRD = 0xC7 -- Exit self refresh to read command ; tRTP = 0x2 -- Internal READ command to PRECHARGE command delay ; tWTR = 0x4 -- Internal WRITE to READ command delay ; tRRD = 0x2 -- ACTIVE to ACTIVE command period mem wr 0x63fd9014 0x00c70092 ;ESDCTL.ESDCFG2 ; Read / WRITE Command Delay ; tDAI = 0x0 -- Field not relevant for DDR2 ; RTW_SAME = 0x2 -- Controls the cycles delay between Read to Write commands in same chip select ; WTR_DIFF = 0x3 -- Controls the cycles delay between Write to Read commands in different chip select ; WTW_DIFF = 0x6 -- Controls the cycles delay between Write to Write commands in different chip select ; RTW_DIFF = 0x2 -- Controls the cycles delay between Read to Write commands in different chip select ; RTR_DIFF = 0x2 -- Controls the cycles delay between Read to Read commands in different chip select mem wr 0x63fd902c 0x000026d2 ;ESDCTL.ESDRWD ; Out of Reset Delays ; tXPR = 0x9F -- DDR2: This value equals a fixed 400 ns by JEDEC ; SDE_to_RST = 0x0 -- DDR2. Not relevant ; RST_to_CKE = 0xE -- DDR2: Time from SDE enable to CKE rise. (JEDEC value is 200 us) mem wr 0x63fd9030 0x009f000e ;ESDCTL.ESDOR ; ESDCTL ODT Timing Control Register ; tAOFPD = 0x2 -- DDR2: ODT turn-off (power down mode) max value ; tAONPD = 0x2 -- DDR2: ODT turn-on (power down mode) max value ; tANPD = 0x2 -- DDR2: ODT to power down entry latency ; tAXPD = 0x7 -- DDR2: ODT power down exit latency ; tODTLon/tAOND = 0x2 -- ODT turn on latency ; tODT_off_idle = 0x0 -- Idle period before turning memory ODT off mem wr 0x63fd9008 0x12272000 ;ESDCTL.ESDOTC ; ESDCTL Power Down Control Register ; PRCT_1 = 0x0 -- Precharge Timer - Chip Select 1 ; PRCT_0 = 0x0 -- Precharge Timer - Chip Select 0 ; tCKE = 0x3 -- CKE minimum pulse width ; PWDT_1 = 0x0 -- Power Down Timer - Chip Select 1 ; PWDT_0 = 0x0 -- Power Down Timer - Chip Select 0 ; SLOW_PD = 0x0 -- DDR2: Slow active power-down. ; BOTH_CS_PD = 0x0 -- ; tCKSRX = 0x2 -- Valid clock requirement before self-refresh exit ; tCKSRE = 0x2 -- Valid clock requirement after self-refresh entry mem wr 0x63fd9004 0x00030012 ;ESDCTL.ESDPDC ; SDRAM Special Command Register ; CMD_ADDR_MSB = 0x4 -- Address 8 LSB bits that match the issued command ; CMD_ADDR_LSB = 0x0 -- Address 8 MSB bits that match the issued command ; CON_REQ = 0x1 -- Configuration request ; WL_EN = 0x0 -- Write Level Enable ; CMD = 0x1 -- Command - Precharge all command ; CMD_CS = 0x0 -- Chip Select - to CS0 ; CMD_BA = 0x0 -- Bank Address - to bank 0 mem wr 0x63fd901c 0x04008010 ;ESDCTL.ESDSCR ; SDRAM Special Command Register ; CMD_ADDR_MSB = 0x0 -- Address 8 LSB bits that match the issued command ; CMD_ADDR_LSB = 0x0 -- Address 8 MSB bits that match the issued command ; CON_REQ = 0x1 -- Configuration request ; WL_EN = 0x0 -- Write Level Enable ; CMD = 0x3 -- Command - Load Mode Register Command ; CMD_CS = 0x0 -- Chip Select - to CS0 ; CMD_BA = 0x2 -- Bank Address - to bank 2 mem wr 0x63fd901c 0x00008032 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008033 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008031 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0b5280b0 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x04008010 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008020 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008020 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0a528030 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x03c68031 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00468031 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x04008018 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0000803a ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0000803b ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008039 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0b528138 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x04008018 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008028 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00008028 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x0a528038 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x03c68039 ;ESDCTL.ESDSCR mem wr 0x63fd901c 0x00468039 ;ESDCTL.ESDSCR ; Refresh Control Register ; REF_CNT = 0x0 -- Refresh Counter ; REF_SEL = 0x1 -- Refresh Selector ; REFR = 0x3 -- Refresh Rate ; START_REF = 0x0 -- Start Refresh cycle mem wr 0x63fd9020 0x00005800 ;ESDCTL.ESDREF ; ODT control register ; ODT3_INT_RES = 0x3 -- On chip ODT byte3 resistor ; ODT2_INT_RES = 0x3 -- On chip ODT byte2 resistor ; ODT1_INT_RES = 0x3 -- On chip ODT byte1 resistor ; ODT0_INT_RES = 0x3 -- On chip ODT byte0 resistor ; ODT_RD_ACT_EN = 0x0 -- Active read CS ODT enable ; ODT_RD_PAS_EN = 0x1 -- Inactive read CS ODT enable. ; ODT_WR_ACT_EN = 0x1 -- Active write CS ODT enable. ; ODT_WR_PAS_EN = 0x1 -- Inactive write CS ODT enable mem wr 0x63fd9058 0x00033337 ;ESDCTL.ODTCTRL mem wr 0x63fd901c 0x00000000 ;ESDCTL.ESDSCR echo "Initialisation completed..." ; This allows PEEDI to flash to the CC(W)MX51 flash. ; use 'flash erase' to erase all flash ; Use 'flash prog tftp:///u-boot.bin bin 0' to program u-boot ; Theoretically you could also flash the kernel and rootfs if you specify the correct addresses, better use u-boot update command. [FLASH_NAND] CHIP = NAND_FLASH CPU = iMX53 ADDR_BASE = 0 FILE = "u-boot.bin", 0x00000000 ERASE_BAD_BLOCKS = NO OOB_INFO = IMX_ECC [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "CCWi-i.MX53> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program card://uboot.bin