;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale i.MX6Q ; Supported board : Sabre Lite board ; ; Revision : 1.1 ; ; Date : August 28, 2013 ; ; NOTE!!! ; The Sabre Lite board has non standard JTAG connector pinout. ; In order to use the Rinetix SWD10 adapter: ; http://download.ronetix.info/peedi/doc/schematics/peedi_swd10.pdf ; You will have to cut or bend pins 7 and 9 of JTAG connector J13, ; so they do not contact the corresponding cable connector holes. ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex-A ; platform is Cortex-A [PLATFORM_Cortex-A] JTAG_CHAIN = 5, 4, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms WAKEUP_TIME = 20 ; delay after power up TIME_AFTER_RESET = 600 ; delay after RST is released ; Firmware after v17.x.x VERBOSE_INFO = 1 ; print info if CORE0_DEBUG_ADDR is not defined CORE0 = CORTEX-A, 2, 0xBA00477 ; TAP is Cortex-A CPU CORE0_DEBUG_ADDR = 0x82150000, 0x82158000 ; Coresight debug component ; Firmware before v17.x.x ;CORE0 = iMX6A, 2, 0xBA00477 ; TAP is Cortex-A CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_MX6 CORE0_WORKSPACE = 0x907000, 0x8000 ; address, lenght in bytes CORE0_FLASH0 = SPI_FLASH CORE0_FLASH1 = CARD_SD3 CORE0_FLASH2 = CARD_SD4 CORE0_PATH = "tftp://192.168.3.60" ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.1.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.1.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_MX6] ; enable cores #1, #2 and #3 mem write 0x020D8000 0x03C00521 ; SRC_SCR ; Configure eCSPI1 using SS1 pin! ; IOMUXC base address: 0x020E0000 ; eCSPI1 base address: 0x02008000 memory write 0x020E0094 0x00000001 memory write 0x020E03A8 0x0001B0B0 memory write 0x020E07F8 0x00000000 memory write 0x020E0098 0x00000001 memory write 0x020E03AC 0x0001B0B0 memory write 0x020E07FC 0x00000000 memory write 0x020E0090 0x00000001 memory write 0x020E03A4 0x0001B0B0 memory write 0x020E07F4 0x00000000 memory write 0x020E009C 0x00000001 memory write 0x020E03B0 0x0001B0B0 memory write 0x020E0804 0x00000000 memory or 0x020C406C 0x00000003 memory and 0x02008008 0xFFFFFFFE ; reset the SPI1 block ;ilko memory write 0x02008008 0x00040028 memory write 0x02008008 0x00041128 ; The burst length is setting automatically in the code ; ---4---- ; Chip select 1 will be asserted! ; ----0--- ; Pre-divider: 1 ; -----0-- ; Post-divider: 1 ; ------2- ; Select master mode for channel 1 ; -------8 ; The SPI burst is started automaticaly memory or 0x02008008 0x00000001 ; re-enable the SPI1 block ;ilko memory write 0x0200800C 0x00020002 memory write 0x0200800C 0x00020000 ; ---2---- Inactive state for data line is low ; -------2 Phase 1 operation of SPI1! ;--------------------------------- ; Configure usdhc3_pads mem write 0x20E02BC 0x0 mem write 0x20E06A4 0x17059 mem write 0x20E02B8 0x10 mem write 0x20E06A0 0x17059 mem write 0x20E02C0 0x0 mem write 0x20E06A8 0x17059 mem write 0x20E02C4 0x0 mem write 0x20E06AC 0x17059 mem write 0x20E02C8 0x0 mem write 0x20E06B0 0x17059 mem write 0x20E02CC 0x0 mem write 0x20E06B4 0x17059 mem write 0x20E02B0 0x5 ;------------------------------- ; Configure usdhc4_pads mem write 0x20E02F8 0x0 mem write 0x20E06E0 0x17059 mem write 0x20E02F4 0x10 mem write 0x20E06DC 0x17059 mem write 0x20E031C 0x1 mem write 0x20E0704 0x17059 mem write 0x20E0320 0x1 mem write 0x20E0708 0x17059 mem write 0x20E0324 0x1 mem write 0x20E070C 0x17059 mem write 0x20E0328 0x1 mem write 0x20E0710 0x17059 mem write 0x20E0314 0x5 ;---------------------------------- mem write 0x020e05a8 0x00000030 mem write 0x020e05b0 0x00000030 mem write 0x020e0524 0x00000030 mem write 0x020e051c 0x00000030 mem write 0x020e0518 0x00000030 mem write 0x020e050c 0x00000030 mem write 0x020e05b8 0x00000030 mem write 0x020e05c0 0x00000030 mem write 0x020e05ac 0x00020030 mem write 0x020e05b4 0x00020030 mem write 0x020e0528 0x00020030 mem write 0x020e0520 0x00020030 mem write 0x020e0514 0x00020030 mem write 0x020e0510 0x00020030 mem write 0x020e05bc 0x00020030 mem write 0x020e05c4 0x00020030 mem write 0x020e056c 0x00020030 mem write 0x020e0578 0x00020030 mem write 0x020e0588 0x00020030 mem write 0x020e0594 0x00020030 mem write 0x020e057c 0x00020030 mem write 0x020e0590 0x00003000 mem write 0x020e0598 0x00003000 mem write 0x020e058c 0x00000000 mem write 0x020e059c 0x00003030 mem write 0x020e05a0 0x00003030 mem write 0x020e0784 0x00000030 mem write 0x020e0788 0x00000030 mem write 0x020e0794 0x00000030 mem write 0x020e079c 0x00000030 mem write 0x020e07a0 0x00000030 mem write 0x020e07a4 0x00000030 mem write 0x020e07a8 0x00000030 mem write 0x020e0748 0x00000030 mem write 0x020e074c 0x00000030 mem write 0x020e0750 0x00020000 mem write 0x020e0758 0x00000000 mem write 0x020e0774 0x00020000 mem write 0x020e078c 0x00000030 mem write 0x020e0798 0x000C0000 mem write 0x021b081c 0x33333333 mem write 0x021b0820 0x33333333 mem write 0x021b0824 0x33333333 mem write 0x021b0828 0x33333333 mem write 0x021b481c 0x33333333 mem write 0x021b4820 0x33333333 mem write 0x021b4824 0x33333333 mem write 0x021b4828 0x33333333 mem write 0x021b0018 0x40081740 mem write 0x021b001c 0x00008000 mem write 0x021b000c 0x555A7975 mem write 0x021b0010 0xFF538E64 mem write 0x021b0014 0x01FF00DB mem write 0x021b002c 0x000026D2 mem write 0x021b0030 0x005B0E21 mem write 0x021b0008 0x09444040 mem write 0x021b0004 0x00025576 mem write 0x021b0040 0x00000027 mem write 0x021b0000 0x831A0000 mem write 0x021b001c 0x04088032 mem write 0x021b001c 0x0408803A mem write 0x021b001c 0x00008033 mem write 0x021b001c 0x0000803B mem write 0x021b001c 0x00428031 mem write 0x021b001c 0x00428039 mem write 0x021b001c 0x09408030 mem write 0x021b001c 0x09408038 mem write 0x021b001c 0x04008040 mem write 0x021b001c 0x04008048 mem write 0x021b0800 0xA1380003 mem write 0x021b4800 0xA1380003 mem write 0x021b0020 0x00005800 mem write 0x021b0818 0x00022227 mem write 0x021b4818 0x00022227 mem write 0x021b083c 0x434B0350 mem write 0x021b0840 0x034C0359 mem write 0x021b483c 0x434B0350 mem write 0x021b4840 0x03650348 mem write 0x021b0848 0x4436383B mem write 0x021b4848 0x39393341 mem write 0x021b0850 0x35373933 mem write 0x021b4850 0x48254A36 mem write 0x021b080c 0x001F001F mem write 0x021b0810 0x001F001F mem write 0x021b480c 0x00440044 mem write 0x021b4810 0x00440044 mem write 0x021b08b8 0x00000800 mem write 0x021b48b8 0x00000800 mem write 0x021b001c 0x00000000 mem write 0x021b0404 0x00011006 ; set the default clock gate to save power mem write 0x020c4068 0x00C03F3F mem write 0x020c406c 0x0030FC03 mem write 0x020c4070 0x0FFFC000 mem write 0x020c4074 0x3FF00000 mem write 0x020c4078 0x00FFF300 mem write 0x020c407c 0x0F0000C3 mem write 0x020c4080 0x000003FF mem write 0x020c4070 0x0FFFCFF3 mem write 0x020c4074 0x3FF0300F mem write 0x020c407c 0x0F0000F3 ; enable AXI cache for VDOA/VPU/IPU ;mem write 0x020e0010 0xF00000CF ; set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 ;mem write 0x020e0018 0x007F007F ;mem write 0x020e001c 0x007F007F [SPI_FLASH] CHIP = SPI25_FLASH nSPI = 1 ; ECSPI1 CPU = iMX6 FILE = "u-boot.nitrogen6q", bin, 0x400 [CARD_SD3] CHIP = CARD CPU = iMX6 SDHC = 3 ; SD3 FILE = "test256k.bin", bin, 2 [CARD_SD4] CHIP = CARD CPU = iMX6 SDHC = 4 ; SD4 ; eMMC relevant partitions: ; 0 - user data ; 1 - boot 1 ; 2 - boot 2 PARTITION = 0 FILE = "test256k.bin", bin, 2 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "imx6> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog