;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale i.MX7 ; Supported board : MCIMX7SABRE ; ; Revision : rev. C ; ; Date : Feb 20, 2017 ; ; Note: ; A7 DDR at 0x80000000 ; M4 OCRAM 128KB at 0x20200000 ; ; PEEDI doesn't connect if a SD card with valid images is inserted ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 20000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms WAKEUP_TIME = 20 ; delay after power up TIME_AFTER_RESET = 600 ; delay after RST is released VERBOSE_INFO = 1 ; print info if CORE0_DEBUG_ADDR is not defined CORE0_DEBUG_ADDR = 0x80070000, 0x80078000 ; CoreSight Debug component CORE0 = Cortex-A, 0, 0x5BA00477 ; TAP is Cortex-A CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_MX7 CORE0_WORKSPACE = 0x907000, 0x8000 ; address, size in bytes CORE0_FLASH0 = QSPI_FLASH CORE0_PATH = "tftp://192.168.3.60" CORE0_FILE = "test.bin", BIN, 0x20000000 CORE1 = Cortex-A, 0, 0x5BA00477 CORE1_DEBUG_ADDR = 0x80072000, 0x80079000 CORE1_STARTUP_MODE = RESET CORE1_ENDIAN = LITTLE CORE1_BREAKMODE = SOFT CORE1_WORKSPACE = 0x907000, 0x8000 ; address, lenght in bytes CORE1_PATH = "tftp://192.168.3.60" CORE2 = Cortex-M CORE2_RESET_MODE = vectreset CORE2_AP_AHB = 4 CORE2_STARTUP_MODE = RESET CORE2_ENDIAN = LITTLE CORE2_BREAKMODE = SOFT CORE2_WORKSPACE = 0x20200000, 0x10000 ; address, lenght in bytes CORE2_PATH = "tftp://192.168.3.60" [INIT_MX7] mem write16 0x30280008 0x0000 ; WDOGx_WMCR, disable watchdog mem write 0x308600b4 0x0a60 ; disable response to debug_req signal for uart1 mem write 0x30390008 0x03 ; SRC_A7RCR1, enable A7_CORE1 mem write 0x3039000C 0xAA ; SRC_M4RCR, enable M4 and reset M4 ; DCD ; board/freescale/mx7dsabresd/imximage.cfg mem write 0x30340004 0x4F400005 ;mem write 0x30360388 0x40000000 ;mem write 0x30360384 0x40000000 mem write 0x30391000 0x00000002 mem write 0x307a0000 0x01040001 mem write 0x307a01a0 0x80400003 mem write 0x307a01a4 0x00100020 mem write 0x307a01a8 0x80100004 mem write 0x307a0064 0x00400046 mem write 0x307a0490 0x00000001 mem write 0x307a00d0 0x00020083 mem write 0x307a00d4 0x00690000 mem write 0x307a00dc 0x09300004 mem write 0x307a00e0 0x04080000 mem write 0x307a00e4 0x00100004 mem write 0x307a00f4 0x0000033f mem write 0x307a0100 0x09081109 mem write 0x307a0104 0x0007020d mem write 0x307a0108 0x03040407 mem write 0x307a010c 0x00002006 mem write 0x307a0110 0x04020205 mem write 0x307a0114 0x03030202 mem write 0x307a0120 0x00000803 mem write 0x307a0180 0x00800020 mem write 0x307a0184 0x02000100 mem write 0x307a0190 0x02098204 mem write 0x307a0194 0x00030303 mem write 0x307a0200 0x00000016 mem write 0x307a0204 0x00080808 mem write 0x307a0210 0x00000f0f mem write 0x307a0214 0x07070707 mem write 0x307a0218 0x0f070707 mem write 0x307a0240 0x06000604 mem write 0x307a0244 0x00000001 mem write 0x30391000 0x00000000 mem write 0x30790000 0x17420f40 mem write 0x30790004 0x10210100 mem write 0x30790010 0x00060807 mem write 0x307900b0 0x1010007e mem write 0x3079009c 0x00000b24 ; DDR Stress Test (3.0.0) ; Read calibration ; DDRPHY_OFFSETR_CON0 (0x30790020) = 0x0A0A0A0A ; ; Write calibration ; DDRPHY_OFFSETW_CON0 (0x30790030) = 0x06060606 mem write 0x30790020 0x0A0A0A0A mem write 0x30790030 0x06060606 mem write 0x30790050 0x01000010 mem write 0x30790050 0x00000010 mem write 0x307900c0 0x0e407304 mem write 0x307900c0 0x0e447304 mem write 0x307900c0 0x0e447306 mem read 0x307900c4 0x1 wait 20 mem write 0x307900c0 0x0e407304 mem write 0x30384130 0x00000000 mem write 0x30340020 0x00000178 mem write 0x30384130 0x00000002 mem write 0x30790018 0x0000000f mem read 0x307a0004 0x1 wait 20 echo echo *** To debug remove the SD card *** ; QSPI clock mem write 0x3038AA80 0x11000001 ; CCM_TARGET_ROOT85 mem write 0x30384154 0x00000003 ; CCGR gate operation ; QSPI mux mem write 0x30330034 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00, ALT2_QSPI_A_DATA0 mem write 0x30330038 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01, ALT2_QSPI_A_DATA1 mem write 0x3033003C 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02, ALT2_QSPI_A_DATA2 mem write 0x30330040 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03, ALT2_QSPI_A_DATA3 mem write 0x30330048 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05, ALT2_QSPI_A_SCLK mem write 0x3033004C 0x2 ; IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06, ALT2_QSPI_A_SS0_B mem write 0x303302A4 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA00 mem write 0x303302A8 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA01 mem write 0x303302AC 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA02 mem write 0x303302B0 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA03 mem write 0x303302B8 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA05 mem write 0x303302BC 0x51 ; SW_PAD_CTL_PAD_EPDC_DATA06 [QSPI_FLASH] CHIP = SPI25_FLASH CPU = FSL_QSPI_IMX7D SPI_CS = 0 FILE = test32k.bin [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "imx7> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog [test] m w 0x907000 0xE1A0000F m w 0x907004 0xE1A0000F m w 0x907008 0xE1A0000F m w 0x90700c 0xE1A0000F set cpsr 0xd3 set pc 0x907000