;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Freescale i.MX8M, i.MX8MM, i.MX8MN ; Supported board : IMX8M-EVK ; ; 0x00000000 - 128 KB, Boot ROM ; 0x00100000 - 8 KB, CAAM (Secure RAM) ; 0x00900000 - 32 KB, OCRAM ; 0x007E0000 - 128 KB, TCML SRAM used by u-boot-spl ; 0x40000000 - 1 GB, DDR ; ; Date : Jan 10, 2019 ; ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 12000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms WAKEUP_TIME = 200 ; delay after power up TIME_AFTER_RESET = 200 ; delay after RST is released ;CORE0_VERBOSE_INFO = 1 ; print info if CORE0_DEBUG_ADDR is not defined CORE0_DEBUG_ADDR = 0x80410000, 0x80420000 ; CoreSight Debug component CORE0 = Cortex-ARMv8_AMP, 0, 0x5BA00477 ; TAP is Cortex-A CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_MX8M ;CORE0_WORKSPACE = 0x40000000, 0x10000 ; LPDDR4 ;CORE0_WORKSPACE = 0x920000, 0x10000 ; iMX8MM, SRAM CORE0_WORKSPACE = 0x910000, 0x10000 ; iMX8M, SRAM CORE0_FLASH0 = FLASH_SD CORE0_FLASH1 = FLASH_EMMC CORE0_PATH = "tftp://192.168.3.60" [] CORE1 = Cortex-M, 0, 0x5BA00477 CORE1_AP_AHB = 4 CORE1_RESET_MODE = vectreset CORE1_STARTUP_MODE = RESET CORE1_ENDIAN = LITTLE CORE1_BREAKMODE = SOFT CORE1_WORKSPACE = 0x20200000, 0x10000 ; address, lenght in bytes CORE1_PATH = "tftp://192.168.3.60" [] CORE2 = Cortex-ARMv8, 0, 0x5BA00477 CORE2_DEBUG_ADDR = 0x80610000, 0x80620000 CORE2_PATH = "tftp://192.168.3.60" CORE3 = Cortex-ARMv8, 0, 0x5BA00477 CORE3_DEBUG_ADDR = 0x80710000, 0x80720000 CORE3_PATH = "tftp://192.168.3.60" CORE4 = Cortex-M, 0, 0xBA00477 CORE4_APSEL = 4 CORE4_STARTUP_MODE = RESET CORE4_ENDIAN = LITTLE CORE4_BREAKMODE = SOFT CORE4_WORKSPACE = 0x20200000, 0x10000 ; OCRAM_128KB CORE4_PATH = "tftp://192.168.3.60" [FLASH_SD] CHIP = CARD CPU = iMX8M ;SDHC = 3 ; SD3, iMX8MM SDHC = 2 ; SD2, SD card, iMX8M FILE = "test256k.bin", bin, 2 [FLASH_EMMC] CHIP = CARD CPU = iMX8M VDD = 1800 ; 1.8V SDHC = 1 ; SD1, eMMC, iMX8M CHIP_WIDTH = 8 FILE = "test256k.bin", bin, 2 [INIT_MX8M] mem write 0x30390008 0x0F ; SRC_A53RCR1: enable A53 cores 1,2,3 mem write 0x3039000C 0xA8 mem write 0x3039000C 0xAA ; SRC_M4RCR: enable and reset M4 core mem write 0x30384524 3 ; CCM_CCGR82_SET, enable USDHC2 clock mem write 0x303300D4 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_CLK mem write 0x303300D8 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_CMD mem write 0x303300DC 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 mem write 0x303300E0 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 mem write 0x303300E4 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 mem write 0x303300E8 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 mem write 0x303300EC 0 ; IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B mem write 0x30384514 3 ; CCM_CCGR81_SET, enable USDHC1 clock mem write 0x303300A0 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_CLK mem write 0x303300A4 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_CMD mem write 0x303300A8 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 mem write 0x303300AC 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 mem write 0x303300B0 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 mem write 0x303300B4 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 mem write 0x303300B8 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 mem write 0x303300BC 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 mem write 0x303300C0 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 mem write 0x303300C4 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 mem write 0x303300C8 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B mem write 0x303300CC 0 ; IOMUXC_SW_MUX_CTL_PAD_SD1_STROBE [mem_mx8mm] ; doesn't work ;###############step 1: DDR clock configuration################ mem write 0x3033023c 0x0 mem write 0x30330240 0x0 mem write 0x303304a4 0xe mem write 0x303304a8 0xe mem write 0x303304fc 0x0 mem write 0x30391000 0x8F00003F ;SRC_DDRC_RCR_ADDR: assert [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n, [4]src_system_rst_b! mem write 0x30391000 0x8F00000F ;SRC_DDRC_RCR_ADDR: deassert [4]src_system_rst_b! mem write 0x3038A088 0x07070000 ;DRAM_APB_CLK_ROOT_CLR mem write 0x3038A084 0x04030000 ;DRAM_APB_CLK_ROOT_SET, dram_apb_clk_root set to source 4 --800MHz/4 ;disable the clock gating mem write 0x303A00EC 0x0000FFFF ;PGC_CPU_MAPPING mem or 0x303A00F8 0x20 ;GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1 mem write 0x30391004 0x8F000000 ;SRC_DDRC_RCR_ADDR ;DRAM_PLL_CONFIG ; The RPA provides the DRAM_PLL_FDIV_CTL0 register (0x30360054) setting for 1500Mhz (0xFA080). ; For frequencies other than 1500Mhz, it is up to the user to create the appropriate register setting for the desired frequency. ; Formula is DDR_freq = [(24MHz x pll_main_div)/(pll_pre_div x 2^pll_post_div)] x 2 mem write 0x30360054 0xFA080 ;DRAM_PLL_FDIV_CTL0: For 1500MHz, pll_main_div = 250, pll_pre_div = 8, pll_post_div = 0 mem write 0x30360058 0x00000000 ;DRAM_PLL_FDIV_CTL1: pll_dsm=0 mem or 0x30360050 0x200 ;DRAM_PLL_GNRL_CTL: pll_rst = 1 mem and 0x30360050 ~0x10 ;DRAM_PLL_GNRL_CTL: pll_bypass = 0 ;mem chkbit1 0x30360050 32 0x80000000 ;DRAM_PLL_GNRL_CTL: check pll_lock=1? wait 100 memory write 0x30391000 0x8F000006 ;;;;;;;;;;;;;;;;step2: DDRC configuration ;;;;;;;;;;;;;;;; mem write 0x3d400304 0x00000001 ;DDRC_DBG1: dis_dq=1, indicates no reads or writes are issued to SDRAM mem write 0x3d400030 0x00000001 ;DDRC_PWRCTL: selfref_en=1, SDRAM enter self-refresh state mem write 0x3D400000 0xA1080020 ;DDRC_MSTR mem write 0x3D400020 0x00000223 ;DDRC_DERATEEN mem write 0x3D400024 0x0003A980 ;DDRC_DERATEINT mem write 0x3D400064 0x005B0087 ;DDRC_RFSHTMG mem write 0x3D4000D0 0xC00305BA ;DDRC_INIT0 mem write 0x3D4000D4 0x00940000 ;DDRC_INIT1 mem write 0x3D4000DC 0x00D4002D ;DDRC_INIT3 mem write 0x3D4000E0 0x00310000 ;DDRC_INIT4 mem write 0x3D4000E8 0x0066004D ;DDRC_INIT6 mem write 0x3D4000EC 0x0016004D ;DDRC_INIT7 mem write 0x3D400100 0x191E1920 ;DDRC_DRAMTMG0 mem write 0x3D400104 0x00060630 ;DDRC_DRAMTMG1 mem write 0x3D40010C 0x00B0B000 ;DDRC_DRAMTMG3 mem write 0x3D400110 0x0E04080E ;DDRC_DRAMTMG4 mem write 0x3D400114 0x02040C0C ;DDRC_DRAMTMG5 mem write 0x3D400118 0x01010007 ;DDRC_DRAMTMG6 mem write 0x3D40011C 0x00000401 ;DDRC_DRAMTMG7 mem write 0x3D400130 0x00020600 ;DDRC_DRAMTMG12 mem write 0x3D400134 0x0C100002 ;DDRC_DRAMTMG13 mem write 0x3D400138 0x0000008D ;DDRC_DRAMTMG14 mem write 0x3D400144 0x0096004B ;DDRC_DRAMTMG17 mem write 0x3D400180 0x02EE0017 ;DDRC_ZQCTL0 mem write 0x3D400184 0x02605B8E ;DDRC_ZQCTL1 mem write 0x3D400188 0x00000000 ;DDRC_ZQCTL2 mem write 0x3D400190 0x0497820A ;DDRC_DFITMG0 mem write 0x3D400194 0x00080303 ;DDRC_DFITMG1 mem write 0x3D4001B4 0x0000170A ;DDRC_DFITMG2 mem write 0x3D4001A0 0xE0400018 ;DDRC_DFIUPD0 mem write 0x3D4001A4 0x00DF00E4 ;DDRC_DFIUPD1 mem write 0x3D4001A8 0x80000000 ;DDRC_DFIUPD2 mem write 0x3D4001B0 0x00000011 ;DDRC_DFIMISC mem write 0x3D4001C0 0x00000001 ;DDRC_DBICTL mem write 0x3D4001C4 0x00000001 ;DDRC_DFI_PHYMSTR ;; the following may be refined by ddrphy training firmware mem write 0x3D4000F4 0x00000C99 ;DDRC_RANKCTL mem write 0x3D400108 0x070E1617 ;DDRC_DRAMTMG2 mem write 0x3D400200 0x0000001F ;DDRC_ADDRMAP0 mem write 0x3D40020C 0x00000000 ;DDRC_ADDRMAP3 mem write 0x3D400210 0x00001F1F ;DDRC_ADDRMAP4 mem write 0x3D400204 0x00080808 ;DDRC_ADDRMAP1 mem write 0x3D400214 0x07070707 ;DDRC_ADDRMAP5 mem write 0x3D400218 0x07070707 ;DDRC_ADDRMAP6 mem write 0x3D400250 0x29001701 ;DDRC_SCHED mem write 0x3D400254 0x0000002C ;DDRC_SCHED1 mem write 0x3D40025C 0x04000030 ;DDRC_PERFHPR1 mem write 0x3D400264 0x900093E7 ;DDRC_PERFLPR1 mem write 0x3D40026C 0x02005574 ;DDRC_PERFWR1 mem write 0x3D400400 0x00000111 ;DDRC_PCCFG mem write 0x3D400408 0x000072FF ;DDRC_PCFGW_0 mem write 0x3D400494 0x02100E07 ;DDRC_PCFGQOS0_0 mem write 0x3D400498 0x00620096 ;DDRC_PCFGQOS1_0 mem write 0x3D40049C 0x01100E07 ;DDRC_PCFGWQOS0_0 mem write 0x3D4004A0 0x00C8012C ;DDRC_PCFGWQOS1_0 ; DDR-200MHz clock configuration mem write 0x3D402020 0x00000021 ;DDRC_FREQ1_DERATEEN mem write 0x3D402024 0x00007D00 ;DDRC_FREQ1_DERATEINT mem write 0x3D402050 0x0020D040 ;DDRC_FREQ1_RFSHCTL0 mem write 0x3D402064 0x000C0012 ;DDRC_FREQ1_RFSHTMG mem write 0x3D4020DC 0x00840000 ;DDRC_FREQ1_INIT3 mem write 0x3D4020E0 0x00310000 ;DDRC_FREQ1_INIT4 mem write 0x3D4020E8 0x0066004D ;DDRC_FREQ1_INIT6 mem write 0x3D4020EC 0x0016004D ;DDRC_FREQ1_INIT7 mem write 0x3D402100 0x0A040305 ;DDRC_FREQ1_DRAMTMG0 mem write 0x3D402104 0x00030407 ;DDRC_FREQ1_DRAMTMG1 mem write 0x3D402108 0x0203060B ;DDRC_FREQ1_DRAMTMG2 mem write 0x3D40210C 0x00505000 ;DDRC_FREQ1_DRAMTMG3 mem write 0x3D402110 0x02040202 ;DDRC_FREQ1_DRAMTMG4 mem write 0x3D402114 0x02030202 ;DDRC_FREQ1_DRAMTMG5 mem write 0x3D402118 0x01010004 ;DDRC_FREQ1_DRAMTMG6 mem write 0x3D40211C 0x00000301 ;DDRC_FREQ1_DRAMTMG7 mem write 0x3D402130 0x00020300 ;DDRC_FREQ1_DRAMTMG12 mem write 0x3D402134 0x0A100002 ;DDRC_FREQ1_DRAMTMG13 mem write 0x3D402138 0x00000013 ;DDRC_FREQ1_DRAMTMG14 mem write 0x3D402144 0x0014000A ;DDRC_FREQ1_DRAMTMG17 mem write 0x3D402180 0x00640004 ;DDRC_FREQ1_ZQCTL0 mem write 0x3D402190 0x03818200 ;DDRC_FREQ1_DFITMG0 mem write 0x3D402194 0x00080303 ;DDRC_FREQ1_DFITMG1 mem write 0x3D4021B4 0x00000100 ;DDRC_FREQ1_DFITMG2 mem write 0x3D4020F4 0x00000C99 ;DDRC_FREQ1_RANKCTL ; DDR-50MHz clock configuration mem write 0x3D403020 0x00000021 ;DDRC_FREQ2_DERATEEN mem write 0x3D403024 0x00001F40 ;DDRC_FREQ2_DERATEINT mem write 0x3D403050 0x0020D040 ;DDRC_FREQ2_RFSHCTL0 mem write 0x3D403064 0x00030005 ;DDRC_FREQ2_RFSHTMG mem write 0x3D4030DC 0x00840000 ;DDRC_FREQ2_INIT3 mem write 0x3D4030E0 0x00310000 ;DDRC_FREQ2_INIT4 mem write 0x3D4030E8 0x0066004D ;DDRC_FREQ2_INIT6 mem write 0x3D4030EC 0x0016004D ;DDRC_FREQ2_INIT7 mem write 0x3D403100 0x0A010102 ;DDRC_FREQ2_DRAMTMG0 mem write 0x3D403104 0x00030404 ;DDRC_FREQ2_DRAMTMG1 mem write 0x3D403108 0x0203060B ;DDRC_FREQ2_DRAMTMG2 mem write 0x3D40310C 0x00505000 ;DDRC_FREQ2_DRAMTMG3 mem write 0x3D403110 0x02040202 ;DDRC_FREQ2_DRAMTMG4 mem write 0x3D403114 0x02030202 ;DDRC_FREQ2_DRAMTMG5 mem write 0x3D403118 0x01010004 ;DDRC_FREQ2_DRAMTMG6 mem write 0x3D40311C 0x00000301 ;DDRC_FREQ2_DRAMTMG7 mem write 0x3D403130 0x00020300 ;DDRC_FREQ2_DRAMTMG12 mem write 0x3D403134 0x0A100002 ;DDRC_FREQ2_DRAMTMG13 mem write 0x3D403138 0x00000005 ;DDRC_FREQ2_DRAMTMG14 mem write 0x3D403144 0x00050003 ;DDRC_FREQ2_DRAMTMG17 mem write 0x3D403180 0x00190004 ;DDRC_FREQ2_ZQCTL0 mem write 0x3D403190 0x03818200 ;DDRC_FREQ2_DFITMG0 mem write 0x3D403194 0x00080303 ;DDRC_FREQ2_DFITMG1 mem write 0x3D4031B4 0x00000100 ;DDRC_FREQ2_DFITMG2 mem write 0x3D4030F4 0x00000C99 ;DDRC_FREQ2_RANKCTL mem write 0x3D400028 0x00000000 ;DDRC_MSTR2 ;RESET DDRC mem write 0x30391000 0x8F000004 ;SRC_DDRC_RCR_ADDR mem write 0x30391000 0x8F000000 ;SRC_DDRC_RCR_ADDR mem write 0x3D400304 0x00000000 ;DDRC_DBG1 mem write 0x3D400030 0x000000A8 ;DDRC_PWRCTL mem write 0x3D400320 0x00000000 ;DDRC_SWCTL mem write 0x3D000000 0x00000001 ;DDRC_DDR_SS_GPR0: LPDDR4 mode mem write 0x3D4001B0 0x00000010 ;DDRC_DDR_DFIMISC:12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en ; DDR PHY DQ lane to memory mapping mem write 0x3C040280 0x00000000 ;DDR_PHY_Dq0LnSel_0 mem write 0x3C040284 0x00000001 ;DDR_PHY_Dq1LnSel_0 mem write 0x3C040288 0x00000002 ;DDR_PHY_Dq2LnSel_0 mem write 0x3C04028C 0x00000003 ;DDR_PHY_Dq3LnSel_0 mem write 0x3C040290 0x00000004 ;DDR_PHY_Dq4LnSel_0 mem write 0x3C040294 0x00000005 ;DDR_PHY_Dq5LnSel_0 mem write 0x3C040298 0x00000006 ;DDR_PHY_Dq6LnSel_0 mem write 0x3C04029C 0x00000007 ;DDR_PHY_Dq7LnSel_0 mem write 0x3C044280 0x00000000 ;DDR_PHY_Dq0LnSel_1 mem write 0x3C044284 0x00000001 ;DDR_PHY_Dq1LnSel_1 mem write 0x3C044288 0x00000003 ;DDR_PHY_Dq2LnSel_1 mem write 0x3C04428C 0x00000004 ;DDR_PHY_Dq3LnSel_1 mem write 0x3C044290 0x00000005 ;DDR_PHY_Dq4LnSel_1 mem write 0x3C044294 0x00000002 ;DDR_PHY_Dq5LnSel_1 mem write 0x3C044298 0x00000007 ;DDR_PHY_Dq6LnSel_1 mem write 0x3C04429C 0x00000006 ;DDR_PHY_Dq7LnSel_1 mem write 0x3C048280 0x00000000 ;DDR_PHY_Dq0LnSel_2 mem write 0x3C048284 0x00000001 ;DDR_PHY_Dq1LnSel_2 mem write 0x3C048288 0x00000003 ;DDR_PHY_Dq2LnSel_2 mem write 0x3C04828C 0x00000002 ;DDR_PHY_Dq3LnSel_2 mem write 0x3C048290 0x00000005 ;DDR_PHY_Dq4LnSel_2 mem write 0x3C048294 0x00000004 ;DDR_PHY_Dq5LnSel_2 mem write 0x3C048298 0x00000007 ;DDR_PHY_Dq6LnSel_2 mem write 0x3C04829C 0x00000006 ;DDR_PHY_Dq7LnSel_2 mem write 0x3C04C280 0x00000000 ;DDR_PHY_Dq0LnSel_3 mem write 0x3C04C284 0x00000001 ;DDR_PHY_Dq1LnSel_3 mem write 0x3C04C288 0x00000002 ;DDR_PHY_Dq2LnSel_3 mem write 0x3C04C28C 0x00000003 ;DDR_PHY_Dq3LnSel_3 mem write 0x3C04C290 0x00000004 ;DDR_PHY_Dq4LnSel_3 mem write 0x3C04C294 0x00000005 ;DDR_PHY_Dq5LnSel_3 mem write 0x3C04C298 0x00000006 ;DDR_PHY_Dq6LnSel_3 mem write 0x3C04C29C 0x00000007 ;DDR_PHY_Dq7LnSel_3 [mem_mx8m] ; 05.03.2021: doesn't work! ; step 1: DDR clock configuration ; change the clock source of dram_apb_clk_root ; follow the power up procedure mem write 0x30391004 0x8f00000F ; SRC_DDRC2_RCR_ADDR mem write 0x30391000 0x8f00000F ; SRC_DDRC_RCR_ADDR mem write 0x30391004 0x8f000000 ; SRC_DDRC2_RCR_ADDR mem write 0x3038A088 0x07070000 ; CCM_TARGET_ROOT_CLR(DRAM_APB_CLK_ROOT) mem write 0x3038A084 0x04030000 ; CCM_TARGET_ROOT_SET(DRAM_APB_CLK_ROOT):MUX=4(system_pll1_800M_clk), PRE_PODF=3 //DRAM_APB_CLK=800/4=200MHz ; disable the clock gating mem write 0x303A00EC 0x0000FFFF ; PGC_CPU_MAPPING memory or 0x303A00F8 0x20 ; GPC_PU_PGC_SW_PUP_REQ: DDR1_SW_PUP_REQ=1 ; default to the frequency point 0 clock mem write 0x3038A080 0x14040000 ; DRAM_PLL_CONFIG ; The RPA provides the HW_DRAM_PLL_CFG2_ADDR register (0x30360068) setting for 1600Mhz (0x00ece580), as well as a few other frequency examples. ; For frequencies other than 1600Mhz, it is up to the user to create the appropriate register setting for the desired frequency. ; Formula is DDR_freq = [REF/DIVR1*2*DIVF1/DIVR2*DIVF2*2/2/DIVQ] x 2 mem write 0x30360068 0x00ece580 ; HW_DRAM_PLL_CFG2_ADDR: For 1600MHz DDR speed, Configure DRAM PLL for 800MHz operation memory and 0x30360060 ~0x80 ; HW_DRAM_PLL_CFG0: SYS_PLL_PD memory or 0x30360060 0x200 ; HW_DRAM_PLL_CFG0: PLL clock enable memory and 0x30360060 ~0x20 ; HW_DRAM_PLL_CFG0: PLL_BYPASS1 disable memory and 0x30360060 ~0x10 ; HW_DRAM_PLL_CFG0: PLL_BYPASS2 disable ;memory chkbit1 0x30360060 0x80000000 ; HW_DRAM_PLL_CFG0: wait PLL lock wait 50 mem write 0x30391000 0x8f000006 ; SRC_DDRC_RCR_ADDR: release [0]ddr1_preset_n, [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n ; step2: DDRC configuration mem write 0x3d400304 0x00000001 ; DDRC_DBG1: dis_dq=1, indicates no reads or writes are issued to SDRAM mem write 0x3d400030 0x00000001 ; DDRC_PWRCTL: selfref_en=1, SDRAM enter self-refresh state mem write 0x3D400000 0xA1080020 ; DDRC_MSTR mem write 0x3D400028 0x00000000 ; DDRC_MSTR2 mem write 0x3D400020 0x00000203 ; DDRC_DERATEEN mem write 0x3D400024 0x0003E800 ; DDRC_DERATEINT mem write 0x3D400064 0x00610090 ; DDRC_RFSHTMG mem write 0x3D4000D0 0xC003061C ; DDRC_INIT0 mem write 0x3D4000D4 0x009E0000 ; DDRC_INIT1 mem write 0x3D4000DC 0x00D4002D ; DDRC_INIT3 mem write 0x3D4000E0 0x00310008 ; DDRC_INIT4 mem write 0x3D4000E8 0x0066004A ; DDRC_INIT6 mem write 0x3D4000EC 0x0016004A ; DDRC_INIT7 mem write 0x3D400100 0x1A201B22 ; DDRC_DRAMTMG0 mem write 0x3D400104 0x00060633 ; DDRC_DRAMTMG1 mem write 0x3D40010C 0x00C0C000 ; DDRC_DRAMTMG3 mem write 0x3D400110 0x0F04080F ; DDRC_DRAMTMG4 mem write 0x3D400114 0x02040C0C ; DDRC_DRAMTMG5 mem write 0x3D400118 0x01010007 ; DDRC_DRAMTMG6 mem write 0x3D40011C 0x00000401 ; DDRC_DRAMTMG7 mem write 0x3D400130 0x00020600 ; DDRC_DRAMTMG12 mem write 0x3D400134 0x0C100002 ; DDRC_DRAMTMG13 mem write 0x3D400138 0x00000096 ; DDRC_DRAMTMG14 mem write 0x3D400144 0x00A00050 ; DDRC_DRAMTMG17 mem write 0x3D400180 0xC3200018 ; DDRC_ZQCTL0 mem write 0x3D400184 0x028061A8 ; DDRC_ZQCTL1 mem write 0x3D400188 0x00000000 ; DDRC_ZQCTL2 mem write 0x3D400190 0x0497820A ; DDRC_DFITMG0 mem write 0x3D400194 0x00080303 ; DDRC_DFITMG1 mem write 0x3D4001A0 0xE0400018 ; DDRC_DFIUPD0 mem write 0x3D4001A4 0x00DF00E4 ; DDRC_DFIUPD1 mem write 0x3D4001A8 0x80000000 ; DDRC_DFIUPD2 mem write 0x3D4001B0 0x00000011 ; DDRC_DFIMISC mem write 0x3D4001B4 0x0000170A ; DDRC_DFITMG2 mem write 0x3D4001C0 0x00000001 ; DDRC_DBICTL mem write 0x3D4001C4 0x00000001 ; DDRC_DFI_PHYMSTR ; the following may be refined by ddrphy training firmware mem write 0x3D4000F4 0x00000639 ; DDRC_RANKCTL mem write 0x3D400108 0x070E1617 ; DDRC_DRAMTMG2 mem write 0x3D400200 0x0000001F ; DDRC_ADDRMAP0 mem write 0x3D40020C 0x00000000 ; DDRC_ADDRMAP3 mem write 0x3D400210 0x00001F1F ; DDRC_ADDRMAP4 mem write 0x3D400204 0x00080808 ; DDRC_ADDRMAP1 mem write 0x3D400214 0x07070707 ; DDRC_ADDRMAP5 mem write 0x3D400218 0x0F070707 ; DDRC_ADDRMAP6 ; DDR-200MHz clock configuration mem write 0x3D402020 0x00000001 ; DDRC_FREQ1_DERATEEN mem write 0x3D402024 0x00007D00 ; DDRC_FREQ1_DERATEINT mem write 0x3D402050 0x0020D040 ; DDRC_FREQ1_RFSHCTL0 mem write 0x3D402064 0x000C0012 ; DDRC_FREQ1_RFSHTMG mem write 0x3D4020DC 0x00840000 ; DDRC_FREQ1_INIT3 mem write 0x3D4020E0 0x00310000 ; DDRC_FREQ1_INIT4 mem write 0x3D4020E8 0x0066004A ; DDRC_FREQ1_INIT6 mem write 0x3D4020EC 0x0016004A ; DDRC_FREQ1_INIT7 mem write 0x3D402100 0x0A040305 ; DDRC_FREQ1_DRAMTMG0 mem write 0x3D402104 0x00030407 ; DDRC_FREQ1_DRAMTMG1 mem write 0x3D402108 0x0203060B ; DDRC_FREQ1_DRAMTMG2 mem write 0x3D40210C 0x00505000 ; DDRC_FREQ1_DRAMTMG3 mem write 0x3D402110 0x02040202 ; DDRC_FREQ1_DRAMTMG4 mem write 0x3D402114 0x02030202 ; DDRC_FREQ1_DRAMTMG5 mem write 0x3D402118 0x01010004 ; DDRC_FREQ1_DRAMTMG6 mem write 0x3D40211C 0x00000301 ; DDRC_FREQ1_DRAMTMG7 mem write 0x3D402130 0x00020300 ; DDRC_FREQ1_DRAMTMG12 mem write 0x3D402134 0x0A100002 ; DDRC_FREQ1_DRAMTMG13 mem write 0x3D402138 0x00000013 ; DDRC_FREQ1_DRAMTMG14 mem write 0x3D402144 0x0014000A ; DDRC_FREQ1_DRAMTMG17 mem write 0x3D402180 0xC0640004 ; DDRC_FREQ1_ZQCTL0 mem write 0x3D402190 0x03818200 ; DDRC_FREQ1_DFITMG0 mem write 0x3D402194 0x00080303 ; DDRC_FREQ1_DFITMG1 mem write 0x3D4021B4 0x00000100 ; DDRC_FREQ1_DFITMG2 ; DDR-50MHz clock configuration mem write 0x3D403020 0x00000001 ; DDRC_FREQ2_DERATEEN mem write 0x3D403024 0x00001F40 ; DDRC_FREQ2_DERATEINT mem write 0x3D403050 0x0020D040 ; DDRC_FREQ2_RFSHCTL0 mem write 0x3D403064 0x00030005 ; DDRC_FREQ2_RFSHTMG mem write 0x3D4030DC 0x00840000 ; DDRC_FREQ2_INIT3 mem write 0x3D4030E0 0x00310000 ; DDRC_FREQ2_INIT4 mem write 0x3D4030E8 0x0066004A ; DDRC_FREQ2_INIT6 mem write 0x3D4030EC 0x0016004A ; DDRC_FREQ2_INIT7 mem write 0x3D403100 0x0A010102 ; DDRC_FREQ2_DRAMTMG0 mem write 0x3D403104 0x00030404 ; DDRC_FREQ2_DRAMTMG1 mem write 0x3D403108 0x0203060B ; DDRC_FREQ2_DRAMTMG2 mem write 0x3D40310C 0x00505000 ; DDRC_FREQ2_DRAMTMG3 mem write 0x3D403110 0x02040202 ; DDRC_FREQ2_DRAMTMG4 mem write 0x3D403114 0x02030202 ; DDRC_FREQ2_DRAMTMG5 mem write 0x3D403118 0x01010004 ; DDRC_FREQ2_DRAMTMG6 mem write 0x3D40311C 0x00000301 ; DDRC_FREQ2_DRAMTMG7 mem write 0x3D403130 0x00020300 ; DDRC_FREQ2_DRAMTMG12 mem write 0x3D403134 0x0A100002 ; DDRC_FREQ2_DRAMTMG13 mem write 0x3D403138 0x00000005 ; DDRC_FREQ2_DRAMTMG14 mem write 0x3D403144 0x00050003 ; DDRC_FREQ2_DRAMTMG17 mem write 0x3D403180 0xC0190004 ; DDRC_FREQ2_ZQCTL0 mem write 0x3D403190 0x03818200 ; DDRC_FREQ2_DFITMG0 mem write 0x3D403194 0x00080303 ; DDRC_FREQ2_DFITMG1 mem write 0x3D4031B4 0x00000100 ; DDRC_FREQ2_DFITMG2 mem write 0x3D400244 0x00000000 ; DDRC_ODTMAP mem write 0x3D400250 0x29001505 ; DDRC_SCHED mem write 0x3D400254 0x0000002C ; DDRC_SCHED1 mem write 0x3D40025C 0x5900575B ; DDRC_PERFHPR1 mem write 0x3D400264 0x90000096 ; DDRC_PERFLPR1 mem write 0x3D40026C 0x1000012C ; DDRC_PERFWR1 mem write 0x3D400300 0x00000016 ; DDRC_DBG0 mem write 0x3D400304 0x00000000 ; DDRC_DBG1 mem write 0x3D40030c 0x00000000 ; DDRC_DBGCMD mem write 0x3d400320 0x00000001 ; DDRC_SWCTL mem write 0x3D40036C 0x00000011 ; DDRC_POISONCFG mem write 0x3D400400 0x00000111 ; DDRC_PCCFG mem write 0x3D400404 0x000010F3 ; DDRC_PCFGR_0 mem write 0x3D400408 0x000072FF ; DDRC_PCFGW_0 mem write 0x3D400490 0x00000001 ; DDRC_PCTRL_0 mem write 0x3D400494 0x00000E00 ; DDRC_PCFGQOS0_0 mem write 0x3D400498 0x0062FFFF ; DDRC_PCFGQOS1_0 mem write 0x3D40049C 0x00000E00 ; DDRC_PCFGWQOS0_0 mem write 0x3D4004A0 0x0000FFFF ; DDRC_PCFGWQOS1_0 ; RESET DDRC mem write 0x30391000 0x8F000004 ; SRC_DDRC_RCR_ADDR mem write 0x30391000 0x8F000000 ; SRC_DDRC_RCR_ADDR mem write 0x3D400030 0x000000A8 ; DDRC_PWRCTL ;memory chkbit1 0x3D400004 0x0223 ; DDRC_STAT: wait to enter Selfrefresh mode wait 50 mem write 0x3D400320 0x00000000 ; DDRC_SWCTL mem write 0x3D000000 0x00000001 ; DDRC_DDR_SS_GPR0: LPDDR4 mode mem write 0x3D4001B0 0x00000010 ; DDRC_DDR_DFIMISC:12:8]dfi_freq, [5]dfi_init_start, [4]ctl_idle_en ; DDR PHY DQ lane to memory mapping mem write 0x3C040280 0x00000000 ; DDR_PHY_Dq0LnSel_0 mem write 0x3C040284 0x00000001 ; DDR_PHY_Dq1LnSel_0 mem write 0x3C040288 0x00000002 ; DDR_PHY_Dq2LnSel_0 mem write 0x3C04028C 0x00000003 ; DDR_PHY_Dq3LnSel_0 mem write 0x3C040290 0x00000004 ; DDR_PHY_Dq4LnSel_0 mem write 0x3C040294 0x00000005 ; DDR_PHY_Dq5LnSel_0 mem write 0x3C040298 0x00000006 ; DDR_PHY_Dq6LnSel_0 mem write 0x3C04029C 0x00000007 ; DDR_PHY_Dq7LnSel_0 mem write 0x3C044280 0x00000000 ; DDR_PHY_Dq0LnSel_1 mem write 0x3C044284 0x00000001 ; DDR_PHY_Dq1LnSel_1 mem write 0x3C044288 0x00000002 ; DDR_PHY_Dq2LnSel_1 mem write 0x3C04428C 0x00000003 ; DDR_PHY_Dq3LnSel_1 mem write 0x3C044290 0x00000004 ; DDR_PHY_Dq4LnSel_1 mem write 0x3C044294 0x00000005 ; DDR_PHY_Dq5LnSel_1 mem write 0x3C044298 0x00000006 ; DDR_PHY_Dq6LnSel_1 mem write 0x3C04429C 0x00000007 ; DDR_PHY_Dq7LnSel_1 mem write 0x3C048280 0x00000000 ; DDR_PHY_Dq0LnSel_2 mem write 0x3C048284 0x00000001 ; DDR_PHY_Dq1LnSel_2 mem write 0x3C048288 0x00000002 ; DDR_PHY_Dq2LnSel_2 mem write 0x3C04828C 0x00000003 ; DDR_PHY_Dq3LnSel_2 mem write 0x3C048290 0x00000004 ; DDR_PHY_Dq4LnSel_2 mem write 0x3C048294 0x00000005 ; DDR_PHY_Dq5LnSel_2 mem write 0x3C048298 0x00000006 ; DDR_PHY_Dq6LnSel_2 mem write 0x3C04829C 0x00000007 ; DDR_PHY_Dq7LnSel_2 mem write 0x3C04C280 0x00000000 ; DDR_PHY_Dq0LnSel_3 mem write 0x3C04C284 0x00000001 ; DDR_PHY_Dq1LnSel_3 mem write 0x3C04C288 0x00000002 ; DDR_PHY_Dq2LnSel_3 mem write 0x3C04C28C 0x00000003 ; DDR_PHY_Dq3LnSel_3 mem write 0x3C04C290 0x00000004 ; DDR_PHY_Dq4LnSel_3 mem write 0x3C04C294 0x00000005 ; DDR_PHY_Dq5LnSel_3 mem write 0x3C04C298 0x00000006 ; DDR_PHY_Dq6LnSel_3 mem write 0x3C04C29C 0x00000007 ; DDR_PHY_Dq7LnSel_3 ; Testing the AMP functionality: ; default AMP mode is BREAK ; run $m ; load a simple program for all cores ; go ; start only core 0 ; go #1 #2 #3 ; start core 1, 2, 3 ; halt ; halt only core 0 ; halt #2 ; halt only core 2 ; halt #a ; halt all cores ; ; amp rhb ; AMP mode RESUME, HALT, BREAK ; run $m ; go ; start all cores ; halt ; halt all cores ; bread add 0x900070 ; add breakpoint for core 0 ; go ; start all cores ; all core halt when core 0 hit the breakpoint ; [m] core 0 mem load mx8_c0_64.bin 0x00920000 set pc 0x00920010 [m90] core 0 mem load mx8_c0_64.bin 0x00900000 set pc 0x00900010 [] core 1 mem load mx8_c1_64.bin 0x00900800 set pc 0x00900810 [] core 2 mem load mx8_c2_64.bin 0x00901000 set pc 0x00901010 core 3 mem load mx8_c3_64.bin 0x00901800 set pc 0x00901810 [r] core 0 m r 0x900000 4 core 1 m r 0x900800 4 [] core 2 m r 0x901000 4 core 3 m r 0x901800 4 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "imx8> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog