;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : OMAP3530 ; Supported board : Beagleboard ; ; Revision : 1.2 ; ; Date : February 7, 2011 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 6, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET RESET_TYPE = ICEPICK-C, 3, 1 ; enable TAP3, warm reset CORE0 = Cortex-A, 1 ; TAP is OMAP3530 CPU CORE0_DEBUG_ADDR = 0x80011000 CORE0_DAPPC = 0xD401D030 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_NAND ; init section for NAND programming without U-BOOT ;CORE0_INIT = INIT_LINUX ; init section with working U-BOOT CORE0_FLASH0 = NAND_XLOAD ; FLASH section parameters CORE0_FLASH1 = NAND_UBOOT ; FLASH section parameters CORE0_WORKSPACE = 0x40200000, 0x10000 ; address, lenght in bytes ;CORE_VECTOR_CATCH_MASK = 0xFE00FCFF ; catch all vectors ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 [INIT_NAND] ; enable module clocks mem write 0x48004a00 0x43FFFE00 ; CM_FCLKEN1_CORE mem write 0x48004a10 0x7FFFFED2 ; CM_ICLKEN1_CORE wait 2 ; following is dumped from the CPU ROM bootloader memory write 0x48004c00+16 0x20 ; WKUP_CM: CM_ICLKEN_WKUP memory write 0x48004c00 0x20 ; CM_FCLKEN_WKUP memory write 0x48314000+16 2 ; WDTIMER2: WD_SYSCONFIG memory write 0x4800291c 0 ; SDRC module semaphore memory write 0x48004c10 0x24 ; WKUP_CM: CM_ICLKEN_WKUP memory write 0x48004000+3328 0x110015 ; CM_CLKEN_PLL memory write 0x48004000+3328 0x110015 ; CM_CLKEN_PLL memory write 0x48004000+2308 0x15 ; CM_CLKEN_PLL_MPU memory write 0x48307000+624 0x40 ; Power and reset manager Module region A memory write 0x48306000+3392 3 memory write 0x48005000+320 0x2030a50 ; PER_CM memory write 0x48004000+2624 0x40a ; CORE_CM memory write 0x48004000+3136 0x4 ; WKUP_CM memory write 0x48004d00 0x310030 ; Clock_Control_Reg_CM memory write 0x48004d00+48 0 memory write 0x48004d00+68 0x6019 memory write 0x48004d00+72 2 memory write 0x48004000+3328 0x370030 memory write 0x48004904 0x35 ; MPU_CM memory write 0x48004904+48 0 memory write 0x48004904+60 0x100000 memory write 0x48004904+64 1 memory write 0x48004904+68 0 memory write 0x48004000+3328 0x300035 ; Clock_Control_Reg_CM memory write 0x48004000+3376 0 memory write 0x48004000+3392 0x8c01900 memory write 0x48004000+3328 0x300037 ; disable WDT2 memory write 0x48314048 0xAAAA memory write 0x48314048 0x5555 ; init GPMC memory write 0x6E000010 0x00000010 memory write 0x6E00001C 0x00000000 memory write 0x6E000040 0x00000000 memory write 0x6E000050 0x00000011 ; init NAND memory write 0x6E000060 0x00001800 memory write 0x6E000064 0x00141400 memory write 0x6E000068 0x00141400 memory write 0x6E00006C 0x0F010F01 memory write 0x6E000070 0x010C1414 memory write 0x6E000074 0x1F0F0A80 memory write 0x6E000078 0x00000870 ; set MMC1 pins mem write16 0x48002144 0x18 ; MMC1_CLK mem write16 0x48002146 0x118 ; MMC1_CMD mem write16 0x48002148 0x118 ; MMC1_DAT0 mem write16 0x4800214A 0x118 ; MMC1_DAT1 mem write16 0x4800214C 0x118 ; MMC1_DAT2 mem write16 0x4800214E 0x118 ; MMC1_DAT3 mem write16 0x48002150 0x118 ; MMC1_DAT4 mem write16 0x48002152 0x118 ; MMC1_DAT5 mem write16 0x48002154 0x118 ; MMC1_DAT6 mem write16 0x48002156 0x118 ; MMC1_DAT7 ; OMAP34xx, OMAP35xx - PBIAS lite mem and 0x48002520 0xFFFFFDFD ; ~0x202 mem or 0x48002520 0x206 mem or 0x48002274 0x01000000 ; DEFCONFIG0 mem or 0x480022D8 0x40 ; DEFCONFIG1 [send] mem write 0x4809C108 0xAA ; r->arg = cmd->cmdarg; mem write 0x4809C10C 0x08000000 ; r->cmd = (cmd->cmdidx << 24) | flags; [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 10000 stop break del all beep 100 100 [NAND_XLOAD] CHIP = NAND_FLASH CMD_BASE = 0x6E00007C ADDR_BASE = 0x6E000080 DATA_BASE = 0x6E000084 ERASE_BAD_BLOCKS = NO OOB_INFO = OMAP3_ECC BURST_MODE = NO FILE = "x-load.bin.ift" bin 0 [NAND_UBOOT] CHIP = NAND_FLASH CMD_BASE = 0x6E00007C ADDR_BASE = 0x6E000080 DATA_BASE = 0x6E000084 ERASE_BAD_BLOCKS = NO OOB_INFO = JFFS2 BURST_MODE = NO FILE = "flash-uboot.bin" 0x80000 ; 22.04.2016 - eMMC programming doesn't work [MMC_CARD] CHIP = CARD CPU = OMAP3 SDHC = 1 FILE = "test32k.bin", bin, 2 PARTITION = 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "omap3> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog