;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Renesas RZG2UL ; Supported board : Ronetix RNX-RZG2UL-OSM ; ; The SPI Flash programming works only in SCIF Download mode ; ; DDR4 at 0x48000000 (first 128MB is reserved for secure area) ; ; Date : Oct 18, 2023 ; ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2013, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = Cortex [PLATFORM_Cortex] JTAG_CHAIN = 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 2000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms WAKEUP_TIME = 200 ; delay after power up TIME_AFTER_RESET = 200 ; delay after RST is released CORE0_VERBOSE_INFO = 0 ; print info if CORE0_DEBUG_ADDR is not defined CORE0_DEBUG_ADDR = 0x10E10000, 0x10E20000 ; CoreSight Debug component CORE0 = Cortex-ARMv8_AMP, 0, 0x5BA00477 ; TAP is Cortex-A CPU CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_RZG2 CORE0_FLASH0 = SPI_FLASH_BL2 CORE0_FLASH1 = SPI_FLASH_FIP CORE0_WORKSPACE = 0x10000, 0x8100 ; total 128KB SRAM, used 32KB CORE0_PATH = "tftp://192.168.3.5" [INIT_RZG2] mem write 0x11000020 24000000 ; SYC, CNTFID0 mem write 0x11000000 1 ; SYC, CNTCR [SPI_FLASH_BL2] CHIP = SPI25_FLASH CPU = RENESAS_RZ FILE = "bl2_bp-rnx-rzg2ul-osm.bin", BIN, 0 [SPI_FLASH_FIP] CHIP = SPI25_FLASH CPU = RENESAS_RZ FILE = "fip.bin", BIN, 0x1D200 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "rzg2> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase 0 0 ; chip erase [prog] flash prog bl2_bp-rnx-rzg2ul-osm.bin 0 flash prog fip.bin 0x1D200