;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for TI TMS570 microcontroller ; ; Ronetix GmbH ; ; Supported devices : TMS570LS04x, TMS570LS1x ; ; TMS570LC43x is currently not supported ; ; Revision : 1.0 ; ; Date : November 30, 2017 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI ; to operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = ARM7, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased ; and are printed on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = CORTEX [PLATFORM_CORTEX] JTAG_CHAIN = 6, 4 ; list of IR length of all ; TAP controller in JTAG chain JTAG_CLOCK = 5000 TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN ; or PUSHPULL ; starting the jtag communication RESET_TIME = 5 ; length of RESET pulse in ms; 0 means no RESET RESET_TYPE = ICEPICK-C, 0, 0 ; enable TAP0, no warm reset TIME_AFTER_RESET = 300 CORE0 = CORTEX-A, 1, 0x4BA00477 CORE0_APSEL = 1 CORE0_DEBUG_ADDR = 0x80001000 CORE0_INIT = INIT_TMS570LS04x ;CORE0_INIT = INIT_TMS570LS1x ;CORE0_INIT = INIT_UNI_TMS570LS1x ;CORE0_INIT = INIT_TMS570LC43xx CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - use software breakpoints ; hard - use hardware breakpoints CORE0_FLASH0 = FLASH_TMS570LS04x CORE0_FLASH1 = FLASH_TMS570LS1x CORE0_FLASH2 = FLASH_TMS570LC43xx CORE0_ENDIAN = BIG ; TMS570 works in BIG endian CORE0_WORKSPACE = 0x08000000, 1024*32 CORE0_FILE = "myfile.bin", BIN, 0x00400000 ; default file CORE0_PATH = "tftp://192.168.3.60" ; default path ;CORE0_PATH = "card://" ; default path [INIT_TMS570LS04x] set r11 0x08000020 ;set frame pointer to free RAM mem write 0x08000020 0x08000028 ;dummy stack frame set sp 0x0800fffc ;set SP to internal SRAM mem write 0xffffff70 0x3F057700 ; Setup pll control register 1 mem write 0xffffff74 0x3FC0723D ; Setup pll control register 2 mem write 0xffffff30 0x00000088 ; Enable PLL(s) to start up or Lock mem and 0xffffffd0 0xFFFFFEFF ; Disable Peripherals before peripheral power-up mem write 0xffffe0a0 0xFFFFFFFF ; Power-up all peripherals mem write 0xffffe0a4 0xFFFFFFFF mem write 0xffffe0a8 0xFFFFFFFF mem write 0xffffe0ac 0xFFFFFFFF mem or 0xffffffd0 0x00000100 ; Enable Peripherals mem write 0xfff87000 0x00000101 ; Setup flash read mode mem write 0xfff87288 0x00000005 ; Setup flash access wait states for bank 7 mem write 0xfff872b8 0x00050002 ; Setup flash access wait states for bank 7 mem write 0xfff87288 0x0000000A ; Disable write access to flash state machine registers mem write 0xfff87040 0x0000C003 ; Setup flash bank power modes mem write 0xffffff88 0x01001008 ; Initialize LPO mem write 0xffffff3c 0x00000020 ; Disable / Enable clock domain wait 100 ; Wait for until clocks are locked mem and 0xffffff70 0xE0FFFFFF ; PLLCTL1 mem or 0xffffff70 0x01000000 ; PLLCTL1 mem write 0xffffff48 0x01010001 ; Setup GCLK, HCLK and VCLK clock source ; Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 mem and 0xffffffd0 0xFFF0FFFF ; systemREG1->CLKCNTRL mem and 0xffffffd0 0xF0FFFFFF ; systemREG1->CLKCNTRL mem write 0xffffff50 0x01090109 ; Setup RTICLK1 and RTICLK2 clocks mem write 0xffffff4c 0x00000909 ; systemREG1->VCLKASRC: Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 mem write 0xffffe140 0x01190119 ; systemREG2->VCLKACON1 mem write 0xffffff00 0x00000000 ; systemREG1->SYSPC1: set ECLK pins functional mode mem write 0xffffff0c 0x00000000 ; mem write 0xffffff04 0x00000001 ; mem write 0xffffff18 0x00000000 ; mem write 0xffffff1c 0x00000000 ; mem write 0xffffff20 0x00000001 ; mem write 0xffffffd4 0x00000007 ; systemREG1->ECPCNTL - Setup ECLK ; Initialization from UNIFLASH ; programming and erasing 5 times slower than with [INIT_TMS570] [INIT_UNI_TMS570LS04x] mem write 0xFFFFF538 0x00000005 ; reset ESM mem write 0xFFFFFF50 0x00000207 ; select clock source 7 for RTICLK (Disable DWD) mem write 0xffffff48 0x00000000 ; set GHVSRC to OSCIN clock source mem write 0xffffff34 0x00000002 ; disable PLL Initialization mem write 0xffffffd0 0x01010000 ; Disable peripherals mem write 0xffffffd0 0x01010100 ; Enable peripherals mem write 0xffffff00 0x00000000 ; disable ECLK output mem write 0xfff7A400 0x00000000 ; disable HTU mem write 0xffffffc0 0x00000000 ; Set RAM wait states to 0 mem write 0xfff87000 0x00000101 ; enable pipeline mode and RWAIT=1 and Address WS=0 mem write 0xfff87288 0x00000005 ; enable write to EWAIT register mem write 0xfff872B8 0x00030002 ; EWAIT=3 mem write 0xfff87008 0x00000005 ; disable error correction and detection mem write 0xfff87040 0x0000ffff ; force active mode for all banks mem write 0xffffffc4 0x0000000a ; "MEMSW='1010' => Flash at 0x00000000, RAM at 0x08000000 ; PLL enabled ; Fast programming, but sometimes requires a couple of power cycles [INIT_TMS570LS1x] mem write 0xffffff70 0x3F057700 ; Setup pll control register 1 mem write 0xffffff74 0x3FC0723D ; Setup pll control register 2 mem write 0xffffe100 0x3F057700 ; Setup pll2 control register mem write 0xffffff30 0x00000088 ; Enable PLL(s) to start up or Lock mem and 0xffffffd0 0xFFFFFEFF ; Disable Peripherals before peripheral power-up mem write 0xffffe0a0 0xFFFFFFFF ; Power-up all peripherals mem write 0xffffe0a4 0xFFFFFFFF mem write 0xffffe0a8 0xFFFFFFFF mem write 0xffffe0ac 0xFFFFFFFF mem or 0xffffffd0 0x00000100 ; Enable Peripherals mem write 0xfff87000 0x00000311 ; Setup flash read mode mem write 0xfff87288 0x00000005 ; Setup flash access wait states for bank 7 mem write 0xfff872b8 0x00050002 ; Setup flash access wait states for bank 7 mem write 0xfff87288 0x0000000A ; Disable write access to flash state machine registers mem write 0xfff87040 0x0000C00F ; Setup flash bank power modes mem write 0xffffff88 0x01001008 ; Initialize LPO mem write 0xffffff3c 0x00000000 ; Disable / Enable clock domain wait 30 ; Wait for until clocks are locked mem and 0xffffff70 0xE0FFFFFF ; PLLCTL1 mem or 0xffffff70 0x00000000 ; PLLCTL1 mem and 0xffffe100 0xE0FFFFFF ; PLLCTL3 mem or 0xffffe100 0x00000000 ; PLLCTL3 mem write 0xffffff48 0x01010001 ; Setup GCLK, HCLK and VCLK clock source mem write 0xffffffd0 0x01010000 ; Disable peripherals mem write 0xffffffd0 0x01010100 ; Enable peripherals mem write 0xffffe13c 0x101 ; systemREG2->VCLK3R mem write 0xffffff50 0x01090109 ; Setup RTICLK1 and RTICLK2 clocks mem write 0xffffff4c 0x00000909 ; systemREG1->VCLKASRC: Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 mem write 0xffffe140 0x01190119 ; systemREG2->VCLKACON1 mem write 0xffffff00 0x00000000 ; systemREG1->SYSPC1: set ECLK pins functional mode mem write 0xffffff0c 0x00000000 ; mem write 0xffffff04 0x00000001 ; mem write 0xffffff18 0x00000000 ; mem write 0xffffff1c 0x00000000 ; mem write 0xffffff20 0x00000001 ; mem write 0xffffffd4 0x00000007 ; systemREG1->ECPCNTL - Setup ECLK ; PLL not enabled ; Slow programming, but works fine [INIT_UNI_TMS570LS1x] mem write 0xFFFFF538 0x00000005 ; reset ESM mem write 0xFFFFFF50 0x00000207 ; select clock source 7 for RTICLK (Disable DWD) mem write 0xffffffd0 0x01010000 ; Disable peripherals mem write 0xffffffd0 0x01010100 ; Enable peripherals mem write 0xfffffa00 0x00070085 ; disable RTP mem write 0xfffff700 0x00010005 ; disable DMM mem write 0xfffff000 0x00000000 ; disable DMA mem write 0xffffff00 0x00000000 ; disable ECLK output mem write 0xfff7A400 0x00000000 ; disable HTU mem write 0xfff7A014 0x00000000 ; disable FTU mem write 0xffffffc0 0x00000000 ; Set RAM wait states to 0 mem write 0xfff87000 0x00000311 ; enable pipeline mode and RWAIT=1 and Address WS=0 mem write 0xfff87288 0x00000005 ; enable write to EWAIT register mem write 0xfff872B8 0x00030002 ; EWAIT=3 mem write 0xfff87008 0x00000005 ; disable error correction and detection mem write 0xfff87040 0x0000ffff ; force active mode for all banks mem write 0xffffffc4 0x0000000a ; "MEMSW='1010' => Flash at 0x00000000, RAM at 0x08000000 [INIT_TMS570LC43xx] mem write 0xffffff34 0x00000042 ; Disable PLL1 and PLL2 wait 50 mem write 0xffffffec 0x00000301 ; Clear Global Status Register mem write 0xffffff70 0x3F074F00 ; Setup pll control register 1 mem write 0xffffff74 0x3FC0703D ; Setup pll control register 2 mem write 0xffffe100 0x1F074F00 ; Setup pll2 control register mem write 0xffffff30 0x0000008C ; Enable PLL(s) to start up or Lock mem and 0xffffffd0 0xFFFFFEFF ; Disable Peripherals before peripheral power-up mem write 0xffff10a0 0xFFFFFFFF mem write 0xffff10a4 0xFFFFFFFF mem write 0xffff10a8 0xFFFFFFFF mem write 0xffff10ac 0xFFFFFFFF mem write 0xfcff10a0 0xFFFFFFFF mem write 0xfcff10a4 0xFFFFFFFF mem write 0xfcff10a8 0xFFFFFFFF mem write 0xfcff10ac 0xFFFFFFFF mem write 0xfff780a0 0xFFFFFFFF mem write 0xfff780a4 0xFFFFFFFF mem write 0xfff780a8 0xFFFFFFFF mem write 0xfff780ac 0xFFFFFFFF mem or 0xffffffd0 0x00000100 ; Enable Peripheral mem write 0xffff1c38 0x83E70B13 ; Enable Pin Muxing mem write 0xffff1c3c 0x95A4F1E0 ; Enable Pin Muxing mem write 0xffff1d10 0x01010101 mem write 0xffff1d14 0x01010101 mem write 0xffff1d18 0x01010101 mem write 0xffff1d1c 0x01010101 mem write 0xffff1d20 0x00010101 mem write 0xffff1d24 0x00000000 mem write 0xffff1d28 0x00000000 mem write 0xffff1d2c 0x00000000 mem write 0xffff1d30 0x01000000 mem write 0xffff1d34 0x01010200 mem write 0xffff1d38 0x01010101 mem write 0xffff1d3c 0x01010101 mem write 0xffff1d40 0x01010101 mem write 0xffff1d44 0x01010101 mem write 0xffff1d48 0x01010101 mem write 0xffff1d4c 0x01010101 mem write 0xffff1d50 0x01010101 mem write 0xffff1d54 0x01010101 mem write 0xffff1d58 0x01010101 mem write 0xffff1d5c 0x01010104 mem write 0xffff1d60 0x01010101 mem write 0xffff1d64 0x08080101 mem write 0xffff1d68 0x01010808 mem write 0xffff1d6c 0x08081008 mem write 0xffff1d70 0x01010101 mem write 0xffff1d74 0x01010101 mem write 0xffff1d78 0x01010101 mem write 0xffff1d7c 0x01010101 mem write 0xffff1d80 0x01010101 mem write 0xffff1d84 0x01010101 mem write 0xffff1d88 0x01010101 mem write 0xffff1d8c 0x01010101 mem write 0xffff1d90 0x01010101 mem write 0xffff1d94 0x01010101 mem write 0xffff1d98 0x01010101 mem write 0xffff1d9c 0x01010101 mem write 0xffff1da0 0x01010101 mem write 0xffff1da4 0x00000101 mem write 0xffff1e50 0x00000001 mem write 0xffff1e54 0x00000000 mem write 0xffff1e58 0x00000000 mem write 0xffff1e5c 0x01000000 mem write 0xffff1e60 0x01010101 mem write 0xffff1e64 0x01010101 mem write 0xffff1e68 0x01010101 mem write 0xffff1e6c 0x01010101 mem write 0xffff1e70 0x00000101 mem write 0xffff1e74 0x01010000 mem write 0xffff1e78 0x01010101 mem write 0xffff1e7c 0x01010101 mem write 0xffff1e80 0x01010101 mem write 0xffff1e84 0x01010101 mem write 0xffff1e88 0x01010101 mem write 0xffff1e8c 0x01010101 mem write 0xffff1e90 0x01010101 mem write 0xffff1e94 0x01010101 mem write 0xffff1e98 0x01010101 mem write 0xffff1e9c 0x00010101 mem and 0xffff1d34 0xFFFFFF00 mem or 0xffff1d34 0x00000001 mem and 0xffff1fdc 0xFFFFFF00 mem or 0xffff1fdc 0x00000001 mem and 0xffff1fdc 0xFFFFFF00 mem or 0xffff1fdc 0x00000001 mem and 0xffff1f90 0x00FFFFFF mem or 0xffff1f90 0x01000000 mem and 0xffff1f94 0xFFFFFF00 mem or 0xffff1f94 0x00000001 mem and 0xffff1fac 0xFFFFFF00 mem or 0xffff1fac 0x00000001 mem and 0xffff1fac 0xFFFF00FF mem or 0xffff1fac 0x00000100 mem and 0xffff1fac 0xFF00FFFF mem or 0xffff1fac 0x00010000 mem and 0xffff1fac 0x00FFFFFF mem or 0xffff1fac 0x01000000 mem and 0xffff1fb0 0xFFFFFF00 mem or 0xffff1fb0 0x00000001 mem and 0xffff1fb0 0xFFFF00FF mem or 0xffff1fb0 0x00000100 mem and 0xffff1fb0 0xFF00FFFF mem or 0xffff1fb0 0x00010000 mem and 0xffff1fa4 0x00FFFFFF mem or 0xffff1fa4 0x01000000 mem and 0xffff1fc0 0xFF00FFFF mem or 0xffff1fc0 0x00010000 mem and 0xffff1fc0 0x00FFFFFF mem or 0xffff1fc0 0x01000000 mem and 0xffff1fc4 0xFFFFFF00 mem or 0xffff1fc4 0x00000001 mem and 0xffff1fc4 0xFFFF00FF mem or 0xffff1fc4 0x00000100 mem and 0xffff1fa0 0xFFFFFF00 mem or 0xffff1fa0 0x00000001 mem and 0xffff1fa0 0xFFFF00FF mem or 0xffff1fa0 0x00000100 mem and 0xffff1fa0 0xFF00FFFF mem or 0xffff1fa0 0x00010000 mem and 0xffff1fa0 0x00FFFFFF mem or 0xffff1fa0 0x01000000 mem and 0xffff1fa4 0xFFFFFF00 mem or 0xffff1fa4 0x00000001 mem and 0xffff1fa4 0xFFFF00FF mem or 0xffff1fa4 0x00000100 mem and 0xffff1fa4 0xFF00FFFF mem or 0xffff1fa4 0x00010000 mem and 0xffff1fb8 0xFF00FFFF mem or 0xffff1fb8 0x00000000 mem and 0xffff1fb8 0x00FFFFFF mem or 0xffff1fb8 0x00000000 mem and 0xffff1fbc 0xFFFFFF00 mem or 0xffff1fbc 0x00000000 mem and 0xffff1fbc 0xFFFF00FF mem or 0xffff1fbc 0x00000000 mem and 0xffff1fbc 0xFF00FFFF mem or 0xffff1fbc 0x00000000 mem and 0xffff1fbc 0x00FFFFFF mem or 0xffff1fbc 0x00000000 mem and 0xffff1fc0 0xFFFFFF00 mem or 0xffff1fc0 0x00000000 mem and 0xffff1fc0 0xFFFF00FF mem or 0xffff1fc0 0x00000000 mem and 0xffff1fb4 0xFFFFFF00 mem or 0xffff1fb4 0x00000000 mem and 0xffff1fb4 0xFFFF00FF mem or 0xffff1fb4 0x00000000 mem and 0xffff1fb4 0xFF00FFFF mem or 0xffff1fb4 0x00000000 mem and 0xffff1fb4 0x00FFFFFF mem or 0xffff1fb4 0x00000000 mem and 0xffff1fb8 0xFFFFFF00 mem or 0xffff1fb8 0x00000000 mem and 0xffff1fb8 0xFFFF00FF mem or 0xffff1fb8 0x00000000 mem and 0xffff1fb8 0xFFFFFF00 mem or 0xffff1fb8 0x00000001 mem and 0xffff1fb8 0xFFFF00FF mem or 0xffff1fb8 0x00000100 mem and 0xffff1fb8 0xFF00FFFF mem or 0xffff1fb8 0x00010000 mem and 0xffff1fb8 0x00FFFFFF mem or 0xffff1fb8 0x01000000 mem and 0xffff1fb8 0xFFFFFF00 mem or 0xffff1fb8 0x00000001 mem and 0xffff1fb8 0xFFFF00FF mem or 0xffff1fb8 0x00000100 mem and 0xffff1fb8 0xFF00FFFF mem or 0xffff1fb8 0x00010000 mem and 0xffff1fb8 0x00FFFFFF mem or 0xffff1fb8 0x01000000 mem and 0xffff1fb8 0xFFFFFF00 mem or 0xffff1fb8 0x00000001 mem and 0xffff1fb8 0xFFFF00FF mem or 0xffff1fb8 0x00000100 mem and 0xffff1fb8 0xFF00FFFF mem or 0xffff1fb8 0x00010000 mem and 0xffff1fb8 0x00FFFFFF mem or 0xffff1fb8 0x01000000 mem and 0xffff1fb8 0xFFFFFF00 mem or 0xffff1fb8 0x00000001 mem and 0xffff1fb8 0xFFFF00FF mem or 0xffff1fb8 0x00000100 mem and 0xffff1fb8 0xFF00FFFF mem or 0xffff1fb8 0x00010000 mem and 0xffff1fb8 0x00FFFFFF mem or 0xffff1fb8 0x01000000 mem or 0xffff1fc8 0x01000000 mem and 0xffff1fc4 0xFF00FFFF mem or 0xffff1fc4 0x00010000 mem and 0xffff1fc4 0x00FFFFFF mem or 0xffff1fc4 0x01000000 mem and 0xffff1fc8 0xFFFFFF00 mem or 0xffff1fc8 0x00000001 mem write 0xffff1f94 0x02020200 mem write 0xffff1f98 0x02020202 mem write 0xffff1f9c 0x00020202 mem write 0xffff1c38 0x00000000 ; Disable Pin Muxing mem write 0xffff1c3c 0x00000000 ; Disable Pin Muxing mem write 0xfff87000 0x00000301 ; Setup flash read mode mem write 0xfff87288 0x00000005 ; Setup flash access wait states for bank 7 mem write 0xfff872b8 0x00090002 mem write 0xfff87288 0x0000000A ; Disable write access to flash state machine registers mem write 0xfff87040 0x0000C00F ; Setup flash bank power modes mem write 0xffffff88 0x01001010 ; Initialize LPO mem write 0xffffe154 0x00000000 ; Setup system clock divider for HCLK mem write 0xffffff3c 0x00000020 ; Disable / Enable clock domain wait 50 ; Wait for until clocks are locked mem and 0xffffff70 0xE0FFFFFF ; the PLL outputs can be sped up mem or 0xffffff70 0x00000000 ; the PLL outputs can be sped up mem and 0xffffe100 0xE0FFFFFF ; Clear and write to the volatile register mem or 0xffffe100 0x00000000 ; Clear and write to the volatile register mem write 0xffffff48 0x01010001 ; Setup GCLK, HCLK and VCLK clock source for normal operation, power down mode and after wakeup mem and 0xffffffd0 0xF0F0FFFF ; Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 mem or 0xffffffd0 0x01010000 ; Setup synchronous peripheral clock dividers for VCLK1, VCLK2, VCLK3 mem and 0xffffe13c 0xFFFFF0F0 mem or 0xffffe13c 0x00000001 mem write 0xffffff50 0x01090109 ; Setup RTICLK1 and RTICLK2 clocks mem write 0xffffff4c 0x00000909 ; Setup asynchronous peripheral clock sources for AVCLK1 and AVCLK2 mem write 0xffffe140 0x00090009 mem write 0xffffff00 0x00000000 ; set ECLK pins functional mode mem write 0xffffff0c 0x00000000 ; set ECLK pins default output value mem write 0xffffff04 0x00000001 ; set ECLK pins output direction mem write 0xffffff18 0x00000000 ; set ECLK pins open drain enable mem write 0xffffff1c 0x00000000 ; set ECLK pins pullup/pulldown enable mem write 0xffffff20 0x00000001 ; set ECLK pins pullup/pulldown select mem write 0xffffffd4 0x00000007 ; Setup ECLK [TEST] ; Fill some code into SRAM set r11 0x08000020 ;set frame pointer to free RAM mem write 0x08000020 0x08000028 ;dummy stack frame set sp 0x0800fffc ;set SP to internal SRAM mem write 0x08000100 0xe1a00000 ;nop mem write 0x08000104 0xe1a00000 ;nop mem write 0x08000108 0xe1a00000 ;nop mem write 0x0800010c 0xe1a00000 ;nop mem write 0x08000110 0xe1a00000 ;nop mem write 0x08000114 0xe1a00000 ;nop mem write 0x08000118 0xe1a00000 ;nop mem write 0x0800011c 0xe1a00000 ;nop mem write 0x08000120 0xe1a00000 ;nop mem write 0x08000124 0xe1a00000 ;nop mem write 0x08000128 0xe1a00000 ;nop mem write 0x0800012c 0xe1a00000 ;nop mem write 0x08000130 0xe1a00000 ;nop mem write 0x08000134 0xe1a00000 ;nop mem write 0x08000138 0xe1a00000 ;nop mem write 0x0800013c 0xeafffffb ;b 0x08000130 set pc 0x08000100 [FLASH_TMS570LS04x] CHIP = TMS570 ; internal flash CPU_CLOCK = 0 ; CPU clock in MHz. If 0, then max HCLK is used FILE = "test32k.bin", BIN, 0 [FLASH_TMS570LS1x] CHIP = TMS570 ; internal flash CPU_CLOCK = 40 ; CPU clock in MHz FILE = "test32k.bin", BIN, 0 [FLASH_TMS570LC43xx] CHIP = TMS570_L2FMC CPU_CLOCK = 40 FILE = "test32k.bin", BIN, 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; CLI over RS232 ;TCP_PORT = 2023 ; serial over telnet [TELNET] PROMPT = "tms570> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ; AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash erase flash prog flash verify [dump_ram] ; dump part of RAM memory dump 0x40000000 0x1000 tftp://192.168.1.1/ram.bin [dump_flash] ; dump part of FLASH memory dump 0x00000000 0x1000 tftp://192.168.1.1/flash.bin