;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : Xilinx Zynq XC7Z020 ; Supported board : ZedBoard ; ; Revision : 1.0 ; ; Date : November 16, 2012 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2012, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.1.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.1.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 [TARGET] PLATFORM = CORTEX [PLATFORM_CORTEX] JTAG_CHAIN = 4, 6 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 1000, 10000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL WAKEUP_TIME = 50 RESET_TIME = 0 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 2000 ; length of RESET pulse in ms; 0 means no RESET VERBOSE_INFO = 0 ; print info if CORE0_DEBUG_ADDR is not defined CORE0 = Cortex-A, 0, 0xBA00477 ; TAP is Cortex-A CPU ;CORE0 = Cortex-A_SMP, 0, 0xBA00477 ; TAP is Cortex-A CPU CORE0_APSEL = 1 ; define AP because automatic detecting is not possible with this CPU CORE0_DEBUG_ADDR = 0x80090000, 0x80098000 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_ZYNQ ; init section with working U-BOOT CORE0_FLASH0 = SPI_FLASH ; SPI bit banging interface CORE0_WORKSPACE = 0xFFFF0000, 0x8000 ; address, length in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.1.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.1.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "test.bin", BIN, 0x20000000 ;CORE1 = Cortex-A, 0, 0xBA00477 ; TAP is Cortex-A CPU ;CORE1_STARTUP_MODE = RESET ; stop the core immediately after reset ;CORE1_ENDIAN = LITTLE ; core is little endian ;CORE1_BREAKMODE = SOFT ; breakpoint mode [INIT_LINUX] break add hard 0xC00087A0 ; kernel break address got by 'nm vmlinux | grep start_kernel' go wait 20000 stop break del all beep 100 100 [INIT_ZYNQ] mem write 0xF8000008 0x0000DF0D ; unlock slcr mem write 0xF8000120 0x1F000100 ; ARM Clk: Divisor = 1, all clk enabled mem write 0xF8000124 0x0C200003 ; DDR2 Clk: Divisor = 3, clk enabled ; SPI mem write 0xf800014c 0x00000121 ; QSPI Divisor = 1 mem write 0xF80001C4 0x00000000 ; 4:2:1 ratio mem write 0xF8000230 0x00000003 ; reset QSPI mem write 0xF8000230 0x00000000 ; reset release QSPI mem write 0xf8000704 0x00001602 ; CS pin mem write 0xf8000708 0x00000602 ; DQ0 / MOSI pin mem write 0xf800070C 0x00000602 ; DQ1 / MISO pin mem write 0xf8000710 0x00000602 ; DQ2 / WP pin mem write 0xf8000714 0x00000602 ; DQ3 / HOLD pin mem write 0xf8000718 0x00000602 ; SCK pin mem write 0xE000D000 0x000A44C1 ; auto start, manual cs, cs deassert, baud div 2, cpol 0, cpha 0 mem write 0xE000D0A0 0x07A0A2EB ; disable LQSPI mem write 0xE000D018 0x00000000 ; no additional delays mem write 0xE000D024 0x000000FF ; mem write 0xE000D038 0x00000000 ; mem write 0xE000D030 0x00000001 ; ;------------------------------------------------------------------------------- ; SPI Flash programming requires boot mode from QSPI: ; QSPI SD ; JP11 - 1 0 ; JP10 - 1 1 ; JP9 - 0 1 ; JP8 - 0 0 ; JP7 - 0 0 ; ; Pinout: ; SCK: MIO6 ; DQ0, MOSI: MIO2 ; DQ1, MISO: MIO3 ; CS: MIO1 [SPI_FLASH] CHIP = SPI25_flash CPU = ZYNQ FILE = "test512k.bin", bin, 0x100000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "zynq> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash prog