;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix GmbH ; ; Supported devices : STM32 L0, L1, F0, F1, F2, F3 F4, H7 ; ; max SWD clock for GD32F427 is 2MHz ; ; Revision : 1.4 ; ; Date : March 5, 2015 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; debug protocol REMOTE_PORT = 2000 ; TCP/IP port ;FLASH = FLASH_GDB ; flash section to be used when programming via gdb FLASH = FLASH_STM32 ; flash section to be used when programming via gdb [TARGET] PLATFORM = Cortex-M ;PLATFORM = Cortex-M_SWD [PLATFORM_Cortex-M] JTAG_CHAIN = 5, 4 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 100, 2000 ; JTAG Clock in [kHz] TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET ; enable if unable to connect to STM32H7 ;RESET_TYPE = RST_NOGATE ; RST is asserted during the connect phase CORE0 = Cortex-M,1 CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_STM32H7 ;CORE0_INIT = INIT_STM32 ;CORE0_INIT = INIT_STM32_L0 ;CORE0_INIT = INIT_STM32_L1 ;CORE0_INIT = INIT_STM32_L4 CORE0_FLASH0 = FLASH_STM32 ; FLASH section CORE0_FLASH1 = FLASH_STM32_DIRECT ; FLASH section CORE0_FLASH2 = FLASH_GDB CORE0_WORKSPACE = 0x20000000, 0x2000 ; workspace for agent programming CORE0_PATH = "tftp://192.168.3.60" ; default path [PLATFORM_Cortex-M_SWD] SWD_CLOCK = 100, 2000 ; SWD Clock in [kHz] ; enable if unable to conenct to STM32H7 RESET_TYPE = RST_NOGATE ; RST is asserted during the connect phase TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET CORE0 = Cortex-M ;CORE0_RESET_MODE = sysresetreq ; software reset: sysresetreq (default) or vectreset CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode CORE0_INIT = INIT_STM32 ; F0, F1, F2 ;CORE0_INIT = INIT_STM32F4 ;CORE0_INIT = INIT_STM32F7 ;CORE0_INIT = INIT_STM32_L0 ;CORE0_INIT = INIT_STM32_L1 ;CORE0_INIT = INIT_STM32_L4 CORE0_FLASH0 = FLASH_STM32 CORE0_FLASH1 = FLASH_STM32_DIRECT CORE0_FLASH2 = FLASH_GDB CORE0_WORKSPACE = 0x20000000, 0x2000 ; workspace for agent programming CORE0_SWO = 0, 2001 CORE0_PATH = "tftp://192.168.3.60" ; default path ;CORE0_PATH = "card:" ;CORE0_PERIODIC_TASK = TASK, 2000 [TASK] mem wr 0x40022000 0x00000012 mem wr 0x40021004 0x001D0002 [INIT_STM32_L0] mem write 0x40021000 0x00000101 ; Set HSION in RCC_CR mem write 0x4002100c 0x00000001 ; Set HSI as SYSCLK [INIT_STM32_L1] mem write 0x40023800 0x00000101 ; Set HSION in RCC_CR mem write 0x40023808 0x00000001 ; Set HSI as SYSCLK [INIT_STM32_L4] ; Stop watchdog counters during halt ; DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP mem write 0xE0042008 0x00001800 ; DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mem or 0xE0042004 0x00000007 mem write 0x40021000 0x00000063 ; Set HSION in RCC_CR mem write 0x40021004 0x40700086 mem write 0x40021008 0 mem write 0x4002100c 0x00001000 ; Set HSI as SYSCLK ; 0x1000 mem write 0x40022000 0x0 ; disable I/D flash cache ; init SWO mem wr 0xE0042004 0x20 ; STM32 DBGMCU_CR: TRACE_IOEN (async mode) mem wr 0xE0040010 2 ; TPIU_ACPR = 1 (SWO prescale 2) mem wr 0xE00400F0 1 ; TPIU_SPPR = 1 (SWO Manchester encoding) mem wr 0xE0040304 0 ; TPIU: disable formatter mem wr 0xE0000FB0 0xC5ACCE55 ; ITM: unlock ITM_TCR mem wr 0xE0000E80 0x10009 ; ITM_TCR: TXENA + ITMENA + TraceBusID=0x1 mem wr 0xE0000E40 0xF ; en. all tracing ports mem wr 0xE0000E00 0xFFFFFFFF ; en. all stimulus ports ; Program option byte with default value [UNPROTECT_GD32F427] m w 0x40003000 0x5555 ; unlock watchdog register m w 0x40003004 0x7 ; prescaler set to 32s m w 0x40003000 0x5555 ; unlock watchdog register m w 0x40003000 0xAAAA ; reset wdog ; unlock FMC_CTL m w 0x40023C04 0x45670123 m w 0x40023C04 0xCDEF89AB ; unlock FMC_OBCTL m w 0x40023C08 0x08192A3B m w 0x40023C08 0x4C5D6E7F m w 0x40023C14 0x2FFFAAEC m w 0x40023C14 0x2FFFAAEE ; start programming ; F0, F1, F2 [INIT_STM32] mem or 0x40021000 0x00010000 ; switch On HSE wait 10 ; wait to stabilize mem wr 0x40021004 0x001D0000 ; config PLL div:1 mul:9 = 72MHz mem or 0x40021000 0x01000000 ; switch On PLL wait 10 ; wait to stabilize mem wr 0x40022000 0x00000012 ; 1ws for FLASH mem wr 0x40021004 0x001D0002 ; select PLL memory or 0xE0042008 0xC00 ; disable watchdog ; init SWO mem wr 0xE0042004 0x20 ; STM32 DBGMCU_CR: TRACE_IOEN (async mode) mem wr 0xE0040010 2 ; TPIU_ACPR = 1 (SWO prescale 2) mem wr 0xE00400F0 1 ; TPIU_SPPR = 1 (SWO Manchester encoding) mem wr 0xE0040304 0 ; TPIU: disable formatter mem wr 0xE0000FB0 0xC5ACCE55 ; ITM: unlock ITM_TCR mem wr 0xE0000E80 0x10009 ; ITM_TCR: TXENA + ITMENA + TraceBusID=0x1 mem wr 0xE0000E40 0xF ; en. all tracing ports mem wr 0xE0000E00 0xFFFFFFFF ; en. all stimulus ports set pc 0 ; set PC and SP to avoid gdb complaining set sp 0x20004FFC ; when FLASH is empty [INIT_STM32F4] mem w 0x40023C00 0x00000001 ; set 1ws for FLASH set pc 0 ; set PC and SP to avoid gdb complaining set sp 0x20004FFC ; when FLASH is empty [INIT_STM32F7] m w 0xE0042004 0x00000007 m w 0xE0042008 0x00001800 m w 0x40023804 0x08002808 ; RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P) m w 0x40023C00 0x00000107 ; FLASH_ACR = PRFTBE | 7(Latency) m w 0x40023800 0x01000000 0 ; RCC_CR |= PLLON wait 10 ; Wait for PLL to lock m w 0x40023808 0x00009400 ; RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2) m w 0x40023808 0x00000002 0 ; RCC_CFGR |= RCC_CFGR_SW_PLL [FLASH_STM32] CHIP = STM32 ; flash chip BASE_ADDR = 0x08000000 ; flash is mapped at 0x08000000 ACCESS_METHOD = AGENT ; use agent programming AUTO_ERASE = NO ; erase before program FILE = test32k.bin 0x8000000 ; file to program ; Select the program parallelism for STM32F2 and STM32F4 ; Valid values: 8, 16, 32, 64 ; 64 bit parallelism can be used only if external Vpp is provided ; By default: 16 bits parallelism F2F4_PSIZE = 32 [FLASH_STM32_DIRECT] CHIP = STM32 ; flash chip BASE_ADDR = 0x08000000 ; flash is mapped at 0x08000000 ACCESS_METHOD = DIRECT ; use direct programming AUTO_ERASE = NO ; erase before program FILE = test32k.bin 0x8000000 ; file to program [FLASH_GDB] ; used when programming via gdb CHIP = STM32 ; flash chip BASE_ADDR = 0x0 ; flash is mapped at 0x00000000 ACCESS_METHOD = AGENT ; use agent programming AUTO_ERASE = NO ; erase before program FILE = test32k.bin 0x0 ; file to program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "stm32> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog [dump_ram] ; dump RAM memory dump 0x20000000 0x5000 tftp://192.168.3.1/ram.bin [dump_flash] ; dump FLASH memory dump 0x00000000 0x20000 tftp://192.168.3.1/flash.bin [m4] set r3 0 mem write16 0x20000010 0x2456 ; movs r4, #86 ; 0x56 mem write16 0x20000012 0x2578 ; movs r5, #120 ; 0x78 mem write16 0x20000014 0xBF00 ; nop mem write16 0x20000016 0xBF00 ; nop mem write16 0x20000018 0x3301 ; adds r3, #1 mem write16 0x2000001a 0xe7f9 ; b.n ; 0x20000010 set pc 0x20000010 ; PEEDI executes scripts with extension '.tcl' as a TCL script ; Alternatively, TCL commands can be placed in a text file with ; extension '.tcl' and started with "run file.tcl" ; Note: ; run $demo.tcl ; start a script defined in PEEDI cfg file ; run file.tcl ; load and execute file with name 'file.tcl' ; ; Alternatively, a TCL statement can be executed within the PEEDI console: ; tcl "set idcode 0x5C001000; set dev_id [mrw $idcode]; puth $dev_id" ; tcl "mon \"mem crc 0 32\"" [demo.tcl] #----------------------------------------------------------------------- # IDCODE address of STM32H7 set idcode 0x5C001000 puth $idcode #----------------------------------------------------------------------- # set 'dev_id' with the value read from address 'idcode' set dev_id [mrw $idcode] puth $dev_id #----------------------------------------------------------------------- # memory write to 0x20000000 set addr 0x20000000 set val 0x11223344 mon "memory write $addr $val" # read back, should print 0x11223344 puth [mrw $addr] #----------------------------------------------------------------------- # memory read from 0x8000000 set x 0x08000000 mon "memory read $x 4" #----------------------------------------------------------------------- # if (dev_id == 0x10016483) # puts "STM32H72x/73x" # else # puts "unknown CPU" if {== $dev_id 0x10016483} {puts "STM32H72x/73x"} \ {== $dev_id 0x20036450} {puts "STM32H74x/75x"} \ {puts "unknown CPU"} if {< 1 2} {puts "OK: A"} {puts "FAIL: B"} if {> 1 2} {puts "FAIL: A"} {puts "OK: B"} if {> 1 2} {puts "OK: A"} #----------------------------------------------------------------------- # x = 0 # if (x == 0) # puts "OK: A" # else # if (x == 1) # puts "FAIL: B" # else # puts "FAIL: C" set x 0; if {== $x 0} \ {puts "OK: A"} \ {== $x 1} \ {puts "FAIL: B"} \ {puts "FAIL: C"} set x 1; if {== $x 0} {puts "FAIL: A"} {== $x 1} {puts "OK: B"} {puts "FAIL: C"} set x 2; if {== $x 0} {puts "FAIL: A"} {== $x 1} {puts "FAIL: B"} {puts "OK: C"} #----------------------------------------------------------------------- # should print '5' # x = 3 # while (x < 5) # x = x + 1 set x 3 while {< $x 0x005} {set x [+ $x 1]} puts $x #----------------------------------------------------------------------- # should print '12' # x = 0 # while (1) # { # x = x + 2 # if (x > 10) # break; # } set x 0 while {== 1 1} \ { \ set x [+ $x 2]; \ if {> $x 10} \ {break} \ } puts $x #----------------------------------------------------------------------- # Bitwise INVERT and AND: should print '0x12340000' # x = x & ~0xFFFF set x [& 0x12345678 ~0xFFFF] puth $x #----------------------------------------------------------------------- # Bitwise OR: should print '0x1234ABCD' # x = x | 0xABCD set x [| $x 0xABCD] puth $x #----------------------------------------------------------------------- # Left shift: should print '0x20' # x = x << 2 set x [<< 8 2] puth $x #----------------------------------------------------------------------- # Right shift: should print '4' # x = x >> 1 set x [>> 8 1] puth $x #----------------------------------------------------------------------- # should print '49' proc square {x} { * $x $x }; puts [square 7] #----------------------------------------------------------------------- # should print '16' set x 4 puts [square $x] #----------------------------------------------------------------------- # should print '42' # (4 * (5 + 7)) - 6 = 42 set a 5; set b 7 puts [- [* 4 [+ $a $b]] 6] #----------------------------------------------------------------------- # execute scripts defined in the cfg file mon {run $script_A} mon {run $script_B} #----------------------------------------------------------------------- # calculate CRC checksum # 'mcrc' returns calculated CRC set addr 0x08000000 set len 1024 set crc [mcrc $addr $len] puth $crc if {== $crc 0xB83AFFF4} \ {puts "CRC: OK"} \ {puts "CRC: FAIL"} #----------------------------------------------------------------------- # test memory region # 'mtest' returns # 0 if successfully tested # 1 if memory test failed set addr 0x0000000 set stat [mtest $addr $len] puth $stat if {== $stat 0} \ {puts "Memory test: OK"} \ {puts "Memory Test: FAIL"} ; just for demo [Script_A] echo "Script A" ; just for demo [Script_B] echo "Script B" [crc.tcl] set addr 0 set len 32 set crc [mcrc $addr $len] puth $crc set stat [mtest $addr $len] puth $stat ; STM32L412 - set option bytes [opt] flash this option 0x20 0x3FFFF1AA reset wait 3000 mem r 0x1fff7800 16