;-------------------------------------------------------------------------- ; ; ; PEEDI sample target configuration file ; ; Ronetix ; ; Supported devices : AC494E - MIPS24k ; ; Revision : 1.0 ; ; Date : Jun 23, 2017 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = CORTEXM3, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased and ; are printed on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt [INIT_MIPS] ; -------------------- ; -------------------- ; GENERAL CPU SETTINGS ; -------------------- ; -------------------- set cp0 12 0x00400000 ; CP0 status reg BEV=1, IE=0 set cp0 13 0x00800000 ; CP0 cause reg IV=0 memory write 0xA8611600 0x03155879 ;PRCR* memory write 0xA8610A20 0x00000004 ;Clock_SCLKCR_reset wait 10 ;10msec memory write 0xA8610A20 0x00000000 ;Clock_SCLKCR* memory write 0xA8610A30 0x00000004 ;Clock_SCLKMD_reset wait 10 ;10msec memory write 0xA8610A30 0x0000B7FE ;Clock_SCLKMD* memory write 0xA8610A40 0x00000004 ;Clock_ECLKCR_reset wait 10 ;10msec memory write 0xA8610A40 0x00000000 ;Clock_ECLKCR memory write 0xA8610A40 0x00000004 ;Clock_ECLKMD_reset wait 10 ;10msec memory write 0xA8610A40 0x000097FE ;Clock_ECLKMD memory write 0xA8610A60 0x00000004 ;Clock_UCLKCR_reset wait 10 ;10msec memory write 0xA8610A60 0x00000000 ;Clock_UCLKCR memory write 0xA8610A70 0x00000004 ;Clock_UCLKMD_reset wait 10 ;10msec memory write 0xA8610A70 0x000037FE ;Clock_UCLKMD memory write 0xA8610A80 0x00000004 ;Clock_LCKCR_reset wait 10 ;10msec memory write 0xA8610A80 0x00000003 ;Clock_LCKCR memory write 0xA8610A90 0x00000004 ;Clock_ACLKCR_reset wait 10 ;10msec memory write 0xA8610A90 0x00008000 ;Clock_ACLKCR memory write 0xA8610A94 0x00000004 ;Clock_AICCLKCR_reset wait 10 ;10msec memory write 0xA8610A94 0x00000001 ;Clock_AICCLKCR memory write 0xA8610AA0 0x00000004 ;Clock_PREUSSBCLKCR wait 10 ;10msec memory write 0xA8610AA0 0x00000000 ;Clock_PREUSSBCLKCR memory write 0xA8610A00 0x08100019 ;Power_up* memory write 0xA8611628 0xA04AA000 ;PINSEL8 memory write 0xA861162C 0x5555AAAA ;PINSEL9 memory write 0xA8611630 0x02A95515 ;PINSEL10 memory write 0xA8611634 0x14550550 ;PINSEL11 memory write 0xA8611638 0x00150555 ;PINSEL12 memory write 0xA8611640 0x1AA00000 ;PINSEL14 memory write 0xA8611644 0x0A299454 ;PINSEL15 memory write 0xA8611648 0x0A000000 ;PINSEL16 memory write 0xA861164c 0xA00000A0 ;PINSEL17 memory write 0xA8611650 0x0000000A ;PINSEL18 memory write 0xA8610910 0x00000000 ;GPIO* memory write 0xA8610914 0x000E0008 ;GPIO* memory write 0xA8610918 0xFE0001FF ;GPIO* memory write 0xA861091C 0x000FFFFF ;GPIO* memory write 0xA8610A08 0xE1F7A007 ;* memory write 0xA8610A10 0x1FFFFFFE ;* memory write 0xA8610A14 0x00038481 ;* ;memory write 0xA8610800 0x40000116 ;BLK_REV memory write 0xA8610804 0xF0000080 ;WAIT_CFG* memory write 0xA8613008 0x00017D23 ;SDRAM_CFG* memory write 0xA861300C 0x0000009C ;SDRAM_REFRASH_CTL* memory write 0xA8610810 0x0C206104 ;CFG_CS_0* memory write 0xA8613020 0x52226920 ;SDRAM_TIME_CTRL* ;memory write 0xA8613024 0x00000009 ;DDR_STATUS memory write 0xA8613028 0x294A8A06 ;DDR_PHY_CTRL* ;memory write 0xA8613030 0x00000000 ; ;memory write 0xA8613034 0x00000000 ; ;memory write 0xA8613038 0x00000000 ; memory write 0xA861303C 0x00000009 ;SDRAM_reflesh* memory write 0xA8610860 0x00000101 ;NAND_Cntrol* ;set config 0x2 [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MIPS32 ; platform is MIPS32 [PLATFORM_MIPS32] JTAG_CHAIN = 5 ; list of TAP controllers in the JTAG chain JTAG_CLOCK = 8000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; 100 length of RESET pulse in ms; 0 means no RESET ;WAKEUP_TIME = 100 ;TIME_AFTER_RESET = 200 CORE0 = MIPS32_M4K, 0, 0x60414000 CORE0_STARTUP_MODE = RESET ;CORE0_STARTUP_MODE = STOP, 4000 CORE0_ENDIAN = LITTLE CORE0_BREAKMODE = soft CORE0_INIT = INIT_MIPS ;CORE0_INIT = INIT_MIPS_BDI CORE0_WORKSPACE = 0x94000000, 0x4000 CORE0_FLASH0 = SST39VF3201 CORE0_FLASH1 = NOR_FLASH CORE0_FLASH2 = SPI_FLASH CORE0_PATH = "tftp://192.168.3.60/mips32_iwatsu" [INIT_MIPS_BDI] mem write 0xA8610804 0xf0000080 ;ASYNC Wait Cycle Config Register mem write 0xA8610808 0x00000000 ; mem write 0xA861080c 0x00000000 ; mem write 0xA8610810 0x0C206104 ;ASYNC CS0 Config Register mem write 0xA8610814 0x05A62D34 ;CFG_CS_3 mem write 0xA8610818 0x05A62D34 ;CFG_CS_4 mem write 0xA861081C 0x05A62D36 ;CFG_CS_5 mem write 0xA8610820 0x00000000 ; mem write 0xA861300c 0x0000009c ;SDRAM Refresh Control Register mem write 0xA8613020 0x52226810 ;SDRAM Timing Register mem write 0xA8613024 0x00000009 ;DDR1 Status Register mem write 0xA8613028 0x294a8a03 ;DDR1 PHY Control Register mem write 0xA861303c 0x0000000b ;SDRAM Self Refresh Exit Timing Register mem write 0xA8613008 0x00004c22 ;SDRAM Config Register mem write 0xA8610a30 0x0000b007 ; mem write 0xA8610a50 0x00009007 ; [NOR_FLASH] CHIP = CFI_FLASH ACCESS_METHOD = DIRECT ; program method auto CHECK_ID = YES ; check chip ID BASE_ADDR = 0xB0000000 ; Backup FLASH FILE = "myfile", BIN, 0x0B000000 ; file to program [SST39VF3201] CHIP = SST39VF3201 CHECK_ID = YES CHIP_WIDTH = 16 CHIP_COUNT = 1 ACCESS_METHOD = DIRECT ; program method auto CHECK_ID = YES ; check chip ID BASE_ADDR = 0xB0000000 ; Backup FLASH FILE = "myfile", BIN, 0x0B000000 ; file to program [SPI_FLASH] CHIP = SPI25_FLASH CPU = GENERIC_SPI CS_ASSERT = 0xFFFFF234 equ 0x00000020 ; clear PA5 CS_RELEASE = 0xFFFFF230 equ 0x00000020 ; set PA5 MOSI_SET = 0xFFFFF230 equ 0x00000002 ; set PA1 MOSI_CLR = 0xFFFFF234 equ 0x00000002 ; clear PA1 SCLK_SET = 0xFFFFF234 equ 0x00000004 ; clear PA2 SCLK_CLR = 0xFFFFF230 equ 0x00000004 ; set PA2 MISO_READ = 0xFFFFF23C and 0x00000001 ; get PA0 FILE = "test.bin", BIN, 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "AC494E> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect ;1 = prog [prog] ;flash erase ;flash prog ;flash program tftp://172.17.124.19/psbl_orchid.bin bin 0xb0000000 erase ;transfer tftp://172.17.124.10/Peedi_AC494E.cfg card://AC494E.cfg ;transfer tftp://172.17.124.10/psbl_orchid.bin card://myfile.bin ; initialize the SDRAM [pbl] mem load pbl.bin bin 0xA0000000 ;mem ver pbl.bin bin 0xA0000000 set pc 0xA0000000 go wait 200 halt [nbl] mem load nbl.bin bin 0x94020000 mem ver nbl.bin bin 0x94020000 set pc 0x94020000