;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC5121 processor ; ; Ronetix ; ; Supported devices : MPC5121 ; ; Board : MPC5121E-ADS ; ; Revision : 1.0 ; ; Date : April 29, 2010 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8300 ; platform is MPC8300 [PLATFORM_MPC8300] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] JTAG_TDO_DELAY = AUTO TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = MPC5121 ; TAP is PowerPC CPU CORE0_INIT = INIT_MPC5121 ;CORE0_INIT = INIT_MPC5121_LINUX CORE0_STARTUP_MODE = reset ;CORE0_BOOT_ADDR = 0x00000100 CORE0_BOOT_ADDR = 0xFFF00100 ; Reset Configuration words: Hi, Lo registers ; The bit order differs from the Freescale's User Manual: ; arg1 bit31 - PCIHOST ; arg1 bit30 - PCI64 ; arg1 bit29 - PCIARB ; .................... ; arg2 bit31 - LBCM ; arg2 bit30 - DDRCM ; .................. ; ; If you want to set RCWHR bit-0 (PCIHOST) and RCWLR bit-1 (DDRCM) regarding ; the Freescale's User Manual, you should use: CORE0_RCW = 0x80000000, 0x40000000 ; ;CORE0_RCW = 0x84600000, 0x04040000 ;override reset configuration words CORE0_MMU_PTBASE = 0x000000F0 CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_BOOT CORE0_FLASH1 = FLASH_BACKUP CORE0_WORKSPACE = 0x30000000, 0x20000 ; workspace for flash programmer ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" ;CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file [INIT_MPC5121_LINUX] break add hard 0xc028b52c ; hardware breakpoint at start_kernel() go ; start U-boot which eventually will start Linux wait 30000 stop ; wait until the kernel halts on the break beep 100 100 ; beep to signal we are ready for debug [INIT_MPC5121] ; init core register set msr 0x00001002 ;MSR : ME,RI mem wr 0xff400000 0xe0000000 ;MABR to 0xe0000000 mem wr 0xe00000c4 0x30000000 ;SRAMBAR to 0x30000000 ; Disable watchdog mem wr 0xe0000904 0x00000000 ;SWCRR ; Enable all clocks mem wr 0xe0000f04 0xffffffff ;SCCR1 mem wr 0xe0000f08 0xffffffff ;SCCR2 ; Initialize CPLD chip select CS2 mem wr 0xe000002C 0xe200e200 ;LPCS2AW : Access Window 0xe2000000...0xe200ffff mem wr 0xe0010008 0x05059010 ;CS2_CONFIG : ; Initialize Flash chip select CS0 mem wr 0xe0000024 0xFC00FFFF ;LPCS0AW : Access Window 0xfc000000...0xffffffff mem wr 0xe0010000 0x05059310 ;CS0_CONFIG : mem wr 0xe0010020 0x01000000 ;CS_CONTROL : BCSR ; Enable Boot Flash writes in CPLD register mem wr8 0xe2000008 0x0A ;enable write to Boot Flash (WP# high) ; Map NFC mem wr 0xe00000C8 0x40000000 ;NFCBAR ; Setup DDR2 DRAM mem wr 0xe000a000 0x00000036 ;IO_CONTROL_MEM: Setup DDR pads for DDR2 mode mem wr 0xe00000a0 0x00000000 ;DDRLAWBAR0: Set DRAM address to 0x00000000 mem wr 0xe00000a4 0x0000001a ;DDRLAWAR0: Set the DRAM size to 256 MB mem wr 0xe0009000 0x30000000 ;Enable DRAM Module mem wr 0xe0009080 0x000777aa ;Setup DRAM Controller Priority Manager mem wr 0xe0009084 0x00000055 mem wr 0xe0009088 0x00000000 mem wr 0xe000908c 0x11111117 mem wr 0xe00090a0 0x7777777a mem wr 0xe0009090 0x444eeeee mem wr 0xe00090a4 0xeeeeeeee mem wr 0xe0009094 0x44444444 mem wr 0xe00090a8 0x44444444 mem wr 0xe0009098 0x55555555 mem wr 0xe00090ac 0x55555558 mem wr 0xe000909c 0x11111111 mem wr 0xe00090b0 0x1111117c mem wr 0xe00090b4 0x33333377 mem wr 0xe00090c8 0x7777eeee mem wr 0xe00090b8 0x11111111 mem wr 0xe00090cc 0x11111111 mem wr 0xe00090bc 0x11111111 mem wr 0xe00090d0 0x11111111 mem wr 0xe00090c0 0x11111111 mem wr 0xe00090d4 0x11111111 mem wr 0xe00090c4 0x11111111 mem wr 0xe00090d8 0x11111111 mem wr 0xe0009000 0xf8604200 ;DDR_SYS_CONFIG mem wr 0xe0009004 0x0000281e ;DDR_TIME_CONFIG0 mem wr 0xe0009008 0x68ec1168 ;DDR_TIME_CONFIG1 mem wr 0xe000900c 0x37a10864 ;DDR_TIME_CONFIG2 mem wr 0xe0009010 0x01380000 ;10x NOP mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01100400 ;PRECHARGE_ALL mem wr 0xe0009010 0x01020000 ;Set EMR2 mem wr 0xe0009010 0x01030000 ;Set EMR3 mem wr 0xe0009010 0x01010000 ;Enable DLL mem wr 0xe0009010 0x01000932 ;Reset DLL mem wr 0xe0009010 0x01100400 ;PRECHARGE_ALL mem wr 0xe0009010 0x01080000 ;2x REFRESH mem wr 0xe0009010 0x01080000 mem wr 0xe0009010 0x01000832 ;Initialize device operation mem wr 0xe0009010 0x01010780 ;Enable OCD default mem wr 0xe0009010 0x01010400 ;Enable OCD exit mem wr 0xe0009010 0x01380000 ;10x NOP mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009010 0x01380000 mem wr 0xe0009004 0x01f4281e ;Start MDDRC mem wr 0xe0009000 0xe8604200 ;This accounts for no pad and no board delay. ;Maybe you have to program some margin if you ;face troubles with reads. I would suggest ;trying 0xe8604a00 or even 0xe8605200. wait 100 [FLASH_BOOT] CHIP = S29GL256N ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 2 ; one chip is used BASE_ADDR = 0xFC000000 FILE = u-boot.bin,BIN,0xFC000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_BACKUP] CHIP = S29GL032AR1/R2 ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 2 ; one chip is used BASE_ADDR = 0xFF800000 FILE = u-boot.bin,BIN,0xFC000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc5121> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog 3 = verify [erase] ; erase flash flash erase [prog] ; program flash flash program u_boot.bin bin 0x80000 flash program [verify] ; verify flash flash verify u-boot.bin