;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC5121 processor ; ; Ronetix ; ; Supported devices : MPC5125 ; ; Board : Custom board ; ; Revision : 1.0 ; ; Date : April 9, 2014 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI ; to operate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = ARM7, 2222-2222-2222-2 ; ; The minimum required licenses are provided when PEEDI is purchased ; and are printed on the bottom side of PEEDI. ; [LICENSE] ; The license keys for one or more PEEDIs can be loaded from an external file FILE = eep:license.txt ;------------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8300 [PLATFORM_MPC8300] JTAG_CHAIN = 8 ; list of IR length of all TAP controller in JTAG chain JTAG_CLOCK = 100, 5000 ; JTAG Clock in [kHz] - 100kHz JTAG clock for init operations and 5MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 500 ; length of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 2000 CORE0 = MPC5121 ; TAP is PowerPC CPU CORE0_INIT = INIT_MPC5125 CORE0_STARTUP_MODE = reset CORE0_BOOT_ADDR = 0xFFF00100 ; Reset Configuration words: Hi, Lo registers ; The bit order differs from the Freescale's User Manual: ; arg1 bit31 - PCIHOST ; arg1 bit30 - PCI64 ; arg1 bit29 - PCIARB ; .................... ; arg2 bit31 - LBCM ; arg2 bit30 - DDRCM ; .................. ; ; If you want to set RCWHR bit-0 (PCIHOST) and RCWLR bit-1 (DDRCM) regarding ; the Freescale's User Manual, you should use: CORE0_RCW = 0x80000000, 0x40000000 ; CORE0_MMU_PTBASE = 0x000000F0 CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = NAND_LOADER CORE0_FLASH1 = NAND_UBOOT CORE0_FLASH2 = NOR_FLASH CORE0_WORKSPACE = 0x00000000, 0x10000 ; workspace for flash programmer ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.0.1" CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file [INIT_MPC5125_LINUX] break add hard 0xc028b52c ; hardware breakpoint at start_kernel() go ; start U-boot which eventually will start Linux wait 30000 stop ; wait until the kernel halts on the break beep 100 100 ; beep to signal we are ready for debug [INIT_MPC5125] ;;;;;;;;;;;;;;;;;;;; ; echo Change IMMR ;;;;;;;;;;;;;;;;;;;; set MBAR 0xFF400000 ; Update MBAR to default value. set MBAR 0xFF400000 ; Update MBAR to default value. mem wr 0xFF400000 0x80000000 ; Update IMMR to 0x80000000. set MBAR 0x80000000 ; Update MBAR to 0x80000000. ;;;;;;;;;;;;;;;;;;;; ; echo Enable Clocks ;;;;;;;;;;;;;;;;;;;; mem wr 0x80000f04 0xFFFFFFFF ; SCCR1 - enable all clocks mem wr 0x80000f08 0xFFFFFFFF ; SCCR2 - enable all clocks mem wr 0x80000F0C 0x0180080C ; SCFR1 - IPS_DIV=1/3. LPC_DIV=1, DIU_DIV=1/3 ;;;;;;;;;;;;;;;;;;;;;;;; ; echo Set up Memory Map ;;;;;;;;;;;;;;;;;;;;;;;; mem wr 0x80000024 0xFE00FFFF ; Set NOR Flash address to 0xFE000000 mem wr 0x800000A0 0x00000000 ; Set DRAM address to 0x00000000 mem wr 0x800000A4 0x0000001B ; Set the DRAM size to 512 MB mem wr 0x800000C4 0x30000000 ; Set SRAM address to 0x30000000 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ENABLE CHIP SELECTS FOR FLASH, GPIB, AND FPGA (2-BYTE PROGRAMMING MODE) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; mem wr 0x80010000 0x000EB100 ; CS0_CONFIG mem wr 0x80010038 0x00000001 ; Set LPC to use TSIZ but not TS mem wr 0x80010020 0x01000000 ; CS_CONTROL : BCSR; Turn on master LPC CS enable mem wr8 0x8000A009 0x43 ; Setup CS2 I/O Control. mem wr8 0x8000A00A 0x03 ; Setup TSIZ1 I/O Control. mem wr8 0x8000A00B 0x03 ; Setup TSIZ2 I/O Control. ; add clock cycle delay in address latch mem wr 0x80010034 0x0000000f ; echo Disable WDT mem wr 0x80000904 0xFFFF0000 ; echo Enable DRAM Module mem wr 0x80009000 0xF0000000 ; setup DDR pads mem wr8 0x8000A000 0x12 ;;;;;;;;;;;;;;;;;;;; ; echo Setup PRIOMAN ;;;;;;;;;;;;;;;;;;;; mem wr 0x80009080 0x000777aa mem wr 0x80009084 0x00000055 mem wr 0x80009088 0x00000000 mem wr 0x8000908C 0x11111117 mem wr 0x800090a0 0x7777777a mem wr 0x80009090 0x444eeeee mem wr 0x800090a4 0xeeeeeeee mem wr 0x80009094 0x44444444 mem wr 0x800090a8 0x44444444 mem wr 0x80009098 0x55555555 mem wr 0x800090ac 0x55555558 mem wr 0x8000909c 0x11111111 mem wr 0x800090b0 0x1111117c mem wr 0x800090b4 0x33333377 mem wr 0x800090c8 0x7777eeee mem wr 0x800090b8 0x11111111 mem wr 0x800090cc 0x11111111 mem wr 0x800090bc 0x11111111 mem wr 0x800090d0 0x11111111 mem wr 0x800090c0 0x11111111 mem wr 0x800090d4 0x11111111 mem wr 0x800090c4 0x11111111 mem wr 0x800090d8 0x11111111 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; echo Init. Micron MT47H64M16LFCK-3 for 200 MHz ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; DDR_SYS_CONFIG - CMDmode=1, row_sel=5, bank_sel=4, SelfRefEn=0, (rdly=2, 1/2=0, 1/4=1)=2.75, wdly=2 mem wr 0x80009000 0xFA804A40 ; DDR_TIME_CONFIG0 - refresh=0, cmd=61, bank_pre=46 mem wr 0x80009004 0x00003c2d ; DDR_TIME_CONFIG1, rfc=26, wr1=7, wrt1=6 ,rrd=2, rc=11, ras=8 mem wr 0x80009008 0x68ec11AA ; DDR_TIME_CONFIG2, rcd=3, faw=10, rtw1=4, ccd=2, rtp=2, rp=3, rpa=4 mem wr 0x8000900c 0x34310864 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; echo Init DDR2 (Micron MT47H64M16LFCK-3) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; mem wr 0x80009010 0x01380000 ;Issue 1 NOP operation while waiting 200 us since clock is stable. mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 mem wr 0x80009010 0x01380000 ; Precharge All mem wr 0x80009010 0x01100400 ; Load Mode to EMR2 to select Self Refresh x1 mem wr 0x80009010 0x01020000 ; Lode Mode to EMR3, Load with all zeros. Does nothing mem wr 0x80009010 0x01030000 ; Load Mode to EMR to enable DLL. mem wr 0x80009010 0x01010000 ; Load Mode to MR for DLL Reset. mem wr 0x80009010 0x01000100 ; Precharge All mem wr 0x80009010 0x01100400 ; Auto Refresh mem wr 0x80009010 0x01080000 ; Auto Refresh mem wr 0x80009010 0x01080000 ; Load Mode to MR. DLL Reset=0, WR=3, TM=0, CAS=3, BT=Seq, BL=4 mem wr 0x80009010 0x01000432 ; Load Mode to EMR to enable OCD default. OCD=7 mem wr 0x80009010 0x010107C0 ; Load Mode to EMR to enable OCD exit mem wr 0x80009010 0x01010440 ; Start MDDRC, DDR_TIME_CONFIG0, refresh=, cmd=, bank_pre= mem wr 0x80009004 0x06183D2E ; DDR_SYS_CONFIG - CMDmode=0, row_sel=, bank_sel=, SelfRefEn=, (rdly=, 1/2=, 1/4=)=, mem wr 0x80009000 0xEa804A40 ; CHOOSE DDR PAD CONFIGURATION ; Setup DDR2 pads for DDR2 mode mem wr8 0x8000A000 0x12 ; Setup DDR pads. mem wr8 0x8000A001 0x01 ; Setup DDR pads. ;;;;;;;;;;;;;;;;;; ; echo Start MDDRC ;;;;;;;;;;;;;;;;;; [test] set MSR 0x0000A000 ;MSR : ME,RI ;;;;;;;;;;;;;;;;;;;;;;;; ; echo Write the MSR ;;;;;;;;;;;;;;;;;;;;;;;; ;set HID0 0x80000000 ; Enable mcp's (EMCP=1) [NOR_FLASH] CHIP = CFI_FLASH BASE_ADDR = 0xFE000000 ; chip is mapped at 0x1000000 ACCESS_METHOD = AGENT ; program method auto FILE = card://test.x, srec [NAND_LOADER] CHIP = NAND_FLASH CPU = MPC5125 ADDR_BASE = 0 CMD_BASE = 0x40000000 ; NFCBAR OOB_INFO = MPC5125_LOADER FILE = tftp://192.168.3.1/u-boot-spl-2k.bin, 0x0 [NAND_UBOOT] CHIP = NAND_FLASH CPU = MPC5125 ADDR_BASE = 0 CMD_BASE = 0x40000000 ; NFCBAR OOB_INFO = MPC5125_UBOOT FILE = tftp://192.168.3.1/u-boot-second-usb.bin, 0x100000 ; list of bad blocks to be marked as bad ;BAD_BLOCKS = 468 ; CAUTION!!! ; Enable erasing of bad blocks ; DO NOT Enable this if you don't know what you are doing ; For more information see the AN006 (www.ronetix.at/an006.html) ;ERASE_BAD_BLOCKS = yes [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc5125> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 80 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = boot 2 = prog [boot] ; erase flash m l tftp://192.168.3.1/u-boot elf mem wr 0x80000000 0xff400000 set mbar 0xff400000 set msr 0 step step step step step step step step step step go [prog] ; program flash flash set 0 flash erase flash program flash set 1 flash program flash verify