;------------------------------------------------------------------------------- ; ; mpc5200_emri.cfg ; ---------------- ; ; PEEDI target configuration file for MPC5200 v1.1 custom board ; ; ; Ronetix ; ; Supported devices : MPC5200 ; ; Revision : 1.0 ; ; Date : Murch 05, 2024 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC5200 ; platform is MPC5200 [PLATFORM_MPC5200] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 8000 ; JTAG Clock in [kHz] TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = MPC5200 ; TAP is MPC5200 CPU CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = SOFT ; breakpoint mode: ; soft - software breakpoint ; hard - use hardware breakpoints instead of software CORE0_INIT = INIT_MPC5200 ; init section for EB55800 board CORE0_FLASH0 = FLASH_BOOT ; flash with primary bootloader CORE0_FLASH1 = FLASH_BACKUP ; flash with backup source code and parameters CORE0_ENDIAN = BIG ; core is big endian CORE0_BOOT_ADDR = 0xFFF00100 ; 0x100 works only if a valid bootloader is present CORE0_WORKSPACE = 0x0, 0x4000 ; SDARAM, start address of workspace for flash programmer ;CORE0_WORKSPACE = 0xF0008000, 0x4000 ; internal SRAM CORE0_PATH = "tftp://192.168.3.5" CORE0_FILE = "myfile.bin", 0 [INIT_MPC5200] ; 128MB SDRAM (2xMT48LC32M16A2) Micron RAM, on CS0: ; t_RFC = 66ns ; t_RP = 20ns ; t_RCD = 20ns ; t_wr = 2clk ; t_ref = 64ms ; ROW = 8K = 8192 ; SYSTEM SETUP: ; SYS_FVCO= 16x33MHz = 528MHz. ; MEM_CLK = XLB_CLK = SYS_PLL_FVCO/4 = 528MHz / 4 = 132MHz (RAM CLK) ; Memory Address Base Register — MBAR + 0x0000 set msr 0x00001002 ; MSR : ME,RI mem write 0x80000000 0x0000f000 ; MBAR : internal registers at 0xf0000000 mem write 0xf0000004 0x0000fff0 ; CS0 Start Address @ 0xfff0_0000 (BOOT Flash) mem write 0xf0000008 0x0000ffff ; CS0 Stop Address @ 0xffff_ffff (Boot FLash) mem write 0xf0000300 0x00043800 ; WaitX=4, AA=1, CE=1, AS=10 (24-bit), (WO=0, RO=0 - Boot Flash is R/W) mem write 0xf000000c 0x00001000 ; CS1 Start Address @ 0x1000_0000 (Backup Flash) mem write 0xf0000010 0x00001fff ; CS1 Stop Address @ 0x1fff_ffff (Backup FLash) mem write 0xf0000304 0x00043800 ; WaitX=4, AA=1, CE=1, AS=10 (24-bit), (WO=0, RO=0 - Backup Flash is R/W) mem write 0xf0000054 0x00030001 ; CSE ( enable CS0, enable CS1, disable CSBOOT; WSE) mem write 0xf0000034 0x00000019 ; SDRAM_CS0 (different from CS0 signal), 64MB @ 0x00000000 mem write 0xf0000038 0x00000000 ; SDRAM_CS1 (different from CS1 signal), disabled @ 0x04000000 mem write 0xf0000108 0xD2322800 mem write 0xf000010c 0x8AD70000 mem write 0xf0000104 0xC14F0000 mem write 0xf0000104 0xC14F0002 mem write 0xf0000104 0xC14F0004 mem write 0xf0000104 0xC14F0004 mem write 0xf0000104 0xC14F0004 mem write 0xf0000100 0x00CD0000 mem write 0xf0000104 0x514F0004 [FLASH_BOOT] CHIP = CFI_FLASH ; flash chip MX29LV040C (512kbyte) ACCESS_METHOD = AGENT ; program method AGENT or DIRECT CHECK_ID = YES ; check chip ID CHIP_WIDTH = 8 ; chip is in 8 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xFFF00000 FILE = "test32k.bin", bin, 0xFFF70000 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_BACKUP] CHIP = CFI_FLASH ; flash chip M29W640DB-N (8Mbyte) ACCESS_METHOD = AGENT ; program method AGENT or DIRECT CHECK_ID = YES ; check chip ID CHIP_WIDTH = 8 ; chip is in 8 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0x10000000 FILE = "test32k.bin", bin, 0 AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc5200> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program