;------------------------------------------------------------------------------- ; ; mpc5566r.cfg ; ------------ ; ; PEEDI target configuration file for Large Engine Module (Ext RAM enabled) ; ; ; Supported devices : MPC5566DEMO eval board (fitted with 14MHz XTAL) ; ; Revision : 1.0 ; ; Date : Dec 15, 2011 ; ;------------------------------------------------------------------------------- ;------------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to oprate. ; ; These licenses must be filled before using this file. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2007, 1111-1111-1111-1 ; KEY = ARM7, 2222-2222-2222-2 ; ; The minimum reqired licenses are provided when PEEDI is purchased and are printed ; on the bottom side of PEEDI. ; ; The license keys for one or more PEEDIs can be loaded from an external file ; FILE = tftp://192.168.3.1/licenses.txt ; [LICENSE] FILE = eep://license.txt ;------------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC5500 ; platform is MPC5500 [PLATFORM_MPC5500] JTAG_CHAIN = 10 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 1000, 20000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 16MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST (JCOMP) output: OPENDRAIN or PUSHPULL RESET_TIME = 100 ; lenght of RESET pulse in ms; 0 means no RESET CORE0 = MPC5XXX_SPE ; TAP is MPC5566 CPU CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = HARD ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE0_INIT = INIT_MPC5566 ; init section for MPC5566EVB board CORE0_FLASH0 = FLASH_MPC ; flash section parameters CORE0_ENDIAN = BIG ; core is big endian CORE0_WORKSPACE_ADDR = 0x40000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x4000 ; length of workspace in bytes CORE0_USE_NEXUS3_ACCESS = NO ; use faster mem access for i given region ;CORE0_USE_NEXUS3_ACCESS = 0x40000000, 0x10000 CORE0_FILE = "myfile.bin", 0x40000000 CORE0_PATH = "tftp://192.168.3.1" [INIT_MPC5566] ; init MMU so virtual addresses equal to physical ; this way we can use Nexus3 module for memory operations ; Setup MMU for for Periph B Modules ; Base address = $FFF0_0000 ; TLB0, 1 MByte Memory Space, Guarded, Don't Cache, All Access set MAS0 0x10000000 set MAS1 0xC0000500 set MAS2 0xFFF0000A set MAS3 0xFFF0003F exec 0x7C0007A4 ; tlbwe ; Set up MMU to put internal Flash at 0... ; Virtual address 0x0 -> Physical address = $0000_0000 ; TLB1, 16 MByte Memory Space, Not Guarded, Cachable, All Access set MAS0 0x10010000 set MAS1 0xC0000700 set MAS2 0x00000000 set MAS3 0x0000003F exec 0x7C0007A4 ; tlbwe ; Set up MMU for External Memory ; Base address = $2000_0000 ; TLB2, 16 MByte Memory Space, Not Guarded, Cachable, All Access set MAS0 0x10020000 set MAS1 0xC0000700 set MAS2 0x20000000 set MAS3 0x2000003F exec 0x7C0007A4 ; tlbwe ; Set up MMU for Internal SRAM ; Base address = $4000_0000 ; TLB3, 256 KByte Memory Space, Not Guarded, Don't Cache, All Access set MAS0 0x10030000 set MAS1 0xC0000400 set MAS2 0x40000008 set MAS3 0x4000003F exec 0x7C0007A4 ; tlbwe ; Set up MMU for Periph A Modules ; Base address = $C3F0_0000 ; TLB4, 1 MByte Memory Space, Not Guarded, Don't Cache, All Access set MAS0 0x10040000 set MAS1 0xC0000500 set MAS2 0xC3F00008 set MAS3 0xC3F0003F exec 0x7C0007A4 ; tlbwe ; Set up MMU for External Memory - SRAM ; Base address = $3F00_0000 ; TLB5, 1MByte Memory Space, Not Guarded, Don't Cache, All Access set MAS0 0x10050000 set MAS1 0xC0000500 set MAS2 0x3f000008 set MAS3 0x3f00003F exec 0x7C0007A4 ; tlbwe ; Set up the pins ; Address bus (A12-A31) PCR 8 - 27 mem wr 0xc3f90050 0x04400440 mem wr 0xc3f90054 0x04400440 mem wr 0xc3f90058 0x04400440 mem wr 0xc3f9005c 0x04400440 mem wr 0xc3f90060 0x04400440 mem wr 0xc3f90064 0x04400440 mem wr 0xc3f90068 0x04400440 mem wr 0xc3f9006c 0x04400440 mem wr 0xc3f90070 0x04400440 mem wr 0xc3f90074 0x04400440 ; Data bus (D0:D15) PCR 28 - 43 mem wr 0xc3f90078 0x04400440 mem wr 0xc3f9007c 0x04400440 mem wr 0xc3f90080 0x04400440 mem wr 0xc3f90084 0x04400440 mem wr 0xc3f90088 0x04400440 mem wr 0xc3f9008c 0x04400440 mem wr 0xc3f90090 0x04400440 mem wr 0xc3f90094 0x04400440 ; config minimum bus control pins ; RD/WR & BDIP PCR 62/63 mem wr 0xc3f900bc 0x04400440 ; WE[0-1] PCR 64-67 mem wr 0xc3f900c0 0x04430443 ; OE & TS mem wr 0xc3f900c8 0x04430443 ; configure the chip selects ; CS[0-3] mem wr 0xc3f90040 0x04430443 mem wr 0xc3f90044 0x04430443 ; Enable external bus interface (16 bit) mem wr 0xc3f84000 0x06010001 ; Set up Memory Controller CS1 @ $3f00_0000 (Must write BR after OR) ; 4 burst beats, use _BE, 16 bit port. 1Mb mem wr 0xc3f8401C 0xff800000 mem wr 0xc3f84018 0x3f000861 ; CLKOUT mem wr16 0xc3f9020a 0x02c0 set spr 63 0x40001000 ; IVPR points to valid memory space set spr 401 0x0 set spr 402 0x0 set spr 403 0x0 set spr 404 0x0 set spr 405 0x0 set spr 406 0x0 set spr 407 0x0 set spr 408 0x0 set spr 409 0x0 set spr 410 0x0 set spr 411 0x0 set spr 412 0x0 set spr 413 0x0 ; MMU data error vector points into valid memory set spr 414 0x0 ; MMU instruction error vector points into valid memory set spr 415 0x0 ; set PLL to 31.5MHz (126MHz / 4) + LOCEN mem wr 0xC3F80000 0x04940000 wait 200 ; set PLL to 126Mhz + LOCEN mem wr 0xC3F80000 0x04840000 wait 200 ; set clock to normal to speedup RAM init clock normal ; init internal RAM (128k) mem wr64 0x40000000 0x0BADF00D0BADF00D 0x4000 [FLASH_MPC] CHIP = MPC5xxx ; internal FLASH FILE = "test32k.bin", BIN, 0 [SERIAL] ; serial port configuration BAUD = 9600 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "mpc5566> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = bootcode [bootcode] ; program boot code flash erase flash prog