;-------------------------------------------------------------------------------
;
;                                   mpc5634M.cfg
;                                   ------------
;
;           PEEDI target configuration file for Freescale MPC5634M
;
;
;   Supported devices   : Freescale MPC5634M
;
;   Board       		: PEMICRO TRK - MPC5634M
;
;   Revision            : 1.0
;
;   Date                : Aug 23, 2012
;
;-------------------------------------------------------------------------------

;-------------------------------------------------------------------------------
; The following section contains licenses that are required for PEEDI to oprate.
;
; These licenses must be filled before using this file.
;
;   Example:
;       [LICENSE]
;       KEY         = UPDATE_24MAY2007, 1111-1111-1111-1
;       KEY         = ARM7,             2222-2222-2222-2
;
; The minimum reqired licenses are provided when PEEDI is purchased and are printed
; on the bottom side of PEEDI.
;
; The license keys for one or more PEEDIs can be loaded from an external file
; FILE = tftp://192.168.3.1/licenses.txt
;

[LICENSE]
FILE = eep://license.txt

;-------------------------------------------------------------------------------

[DEBUGGER]
PROTOCOL                = gdb_remote    ; gdb remote
REMOTE_PORT             = 2000          ; TCP/IP port

[TARGET]
PLATFORM                = MPC5500

[PLATFORM_MPC5500]
JTAG_CHAIN              = 10            ; list of IR lenght of all TAP controller in JTAG chain
JTAG_CLOCK              = 1000, 12000   ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 12MHz for normal work
TRST_TYPE               = PUSHPULL      ; type of TRST (JCOMP) output: OPENDRAIN or PUSHPULL
RESET_TIME              = 20            ; lenght of RESET pulse in ms; 0 means no RESET
TIME_AFTER_RESET 		= 250

CORE0                   = MPC5XXX_SPE
CORE0_STARTUP_MODE      = RESET
CORE0_BREAKMODE         = HARD          ; breakpoint mode:
                                        ; soft - software breakpiont
                                        ; hard - use hardware breakpoints instead of software
CORE0_INIT              = INIT_MPC5634M ; init section
CORE0_FLASH0            = FLASH_MPC     ; flash section parameters
CORE0_ENDIAN            = BIG           ; core is big endian
CORE0_WORKSPACE_ADDR    = 0x40000000    ; start address of workspace for flash programmer
CORE0_WORKSPACE_LEN     = 0x10000       ; length of workspace in bytes
CORE0_FILE              = mpc5634m.elf
CORE0_PATH              = "tftp://192.168.3.60"

[INIT_MPC5634M]
; init MMU so virtual addresses equal to physical
; this way we can use Nexus3 module for memory operations

; Setup MMU for for Periph B Modules
; Base address = $FFF0_0000
; TLB0, 1 MByte Memory Space, Guarded, Don't Cache, All Access
set MAS0 0x10000000
set MAS1 0xC0000500
set MAS2 0xFFF0000A
set MAS3 0xFFF0003F
exec 0x7C0007A4 ; tlbwe

; Set up MMU to put internal Flash at 0...
; Virtual address 0x0 -> Physical address = $0000_0000
; TLB1, 16 MByte Memory Space, Not Guarded, Cachable, All Access
set MAS0 0x10010000
set MAS1 0xC0000700
set MAS2 0x00000000
set MAS3 0x0000003F
exec 0x7C0007A4 ; tlbwe

; Set up MMU for Periph A Modules
; Base address = $C3F0_0000
; TLB4, 1 MByte Memory Space, Not Guarded, Don't Cache, All Access
set MAS0 0x10020000
set MAS1 0xC0000500
set MAS2 0xC3F00008
set MAS3 0xC3F0003F
exec 0x7C0007A4 ; tlbwe

; Set up MMU for Internal SRAM
; Base address = $4000_0000
; TLB3, 256 KByte Memory Space, Not Guarded, Don't Cache, All Access
set MAS0 0x10030000
set MAS1 0xC0000400
set MAS2 0x40000008			; BookE
set MAS3 0x4000003F
exec 0x7C0007A4 ; tlbwe

; disable Software Watchdog
mem wr 0xfff38010 0xC520
mem wr 0xfff38010 0xD928
mem wr 0xfff38000 0xFF00010A

set spr 63  0x40001000    ; IVPR points to valid memory space
set spr 401 0x0
set spr 402 0x0
set spr 403 0x0
set spr 404 0x0
set spr 405 0x0
set spr 406 0x0
set spr 407 0x0
set spr 408 0x0
set spr 409 0x0
set spr 410 0x0
set spr 411 0x0
set spr 412 0x0
set spr 413 0x0   ; MMU data error vector points into valid memory
set spr 414 0x0   ; MMU instruction error vector points into valid memory
set spr 415 0x0
set spr 528 0x0
set spr 529 0x0
set spr 530 0x0

; set PLL to 31.5MHz (126MHz / 4) + LOCEN
mem wr 0xC3F80000 0x04940000
wait 200

; set PLL to 126Mhz + LOCEN
mem wr 0xC3F80000 0x04840000
wait 200

; set clock to normal to speedup RAM init
clock normal

; init internal RAM (94k)
mem wr64 0x40000000 0x0BADF00D0BADF00D 0x2F00


[FLASH_MPC]
CHIP                = MPC5XXX 
AGENT_MODE 			= BOOKE
FILE                = "test1536k.bin", 0x0


[SERIAL]                                ; serial port configuration
BAUD                = 9600
STOP_BITS           = 1
PARITY              = NONE
TCP_PORT            = 0                 ; enable CLI over RS232
;TCP_PORT           = 2023              ; enable serial over TCP/IP

[TELNET]
PROMPT              = "mpc5634m> "      ; telnet prompt
;BACKSPACE          = 127               ; comment out for autodetect

[DISPLAY]
BRIGHTNESS          = 20                ; LED indicator brightness
VOLUME              = 25                ; zummer volume

[ACTIONS]                               ; user defined scripts
1 = erase
2 = prog

[erase]
flash erase

[prog]
flash prog