;------------------------------------------------------------------------------- ; ; mpc5748g.cfg ; ------------ ; ; PEEDI target configuration file for Freescale MPC5748G CPU ; ; ; Ronetix ; ; Supported devices : MPC5748G ; ; MPC574xB/C/G (Calypso3M/6M) ; MPC5744B MPC5745B MPC5746B MPC5744C MPC5745C MPC5746C ; MPC5747C MPC5748C MPC5746G MPC5747G MPC5748G ; ; ; Board : MPC5748G-DEVKIT ; ; Revision : 1.0 ; ; Date : May 11, 2018 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;------------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2020, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC5500 [PLATFORM_MPC5500] MPC5XXX_AUX_TAP_CMD = 6, 0x28 ; select core 0, AUX_TAP_Z4a JTAG_CHAIN = 10 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 4000, 25000 ; JTAG Clock in [kHz] - 4MHz for init operations and 25MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST (JCOMP) output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 CORE0 = MPC5XXX CORE0_AUX_TAP_CMD = 6, 0x28 ; select core 0, AUX_TAP_Z4a CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = soft ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software CORE0_INIT = INIT_MPC57XX ; init section for MPC5604 CORE0_FLASH0 = FLASH_MPC5XXX ; flash section parameters CORE0_ENDIAN = BIG ; core is big endian CORE0_WORKSPACE_ADDR = 0x40000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x4000 ; length of workspace in bytes CORE0_USE_NEXUS3_ACCESS = NO ; use faster mem access for a given region CORE0_PATH = "tftp://192.168.3.60" ;CORE0_PATH = "card://" CORE0_FILE = "myfile.bin", 0x40000000 CORE1 = MPC5XXX CORE1_AUX_TAP_CMD = 6, 0x29 ; select core 1, AUX_TAP_Z4b CORE1_STARTUP_MODE = RESET CORE1_BREAKMODE = soft ; breakpoint mode: ; soft - software breakpiont ; hard - use hardware breakpoints instead of software ;CORE1_INIT = INIT_MPC57XX ; init section for MPC5604 CORE1_ENDIAN = BIG ; core is big endian CORE1_USE_NEXUS3_ACCESS = NO ; use faster mem access for a given region CORE1_PATH = "tftp://192.168.3.60" CORE1_FILE = "myfile.bin", 0x40000000 CORE1_WORKSPACE = 0x40000000, 0x4000 [INIT_MPC57XX] ; disable SWT WD timer mem write 0xFC054010 0x0000C520 mem write 0xFC054010 0x0000D928 mem write 0xFC054000 0xFF00000A set IVPR 0x40000000 ; IVPR points to valid memory space ; Select FIRC 16MHz m w 0xFFFB01C0 0x01000000 ; MC_CGM_AC5_SC ; Enable output clock devided m w 0xFFFB08C8 0x80000000 ; MC_CGM_AC6_DC0->DE ; Divide output clock by 20 m w 0xFFFB08C8 0x00013000 ; MC_CGM_AC6_DC0->DIV ; Configure RunPeripheralConfiguration registers in ME_RUN_PC0 m w 0xFFFB8080 0x00000008 ; MC_ME_RUN_PC0->DRUN ; Enable external oscilator m w 0xFFFB802C 0x00000020 ; MC_ME_DRUN_MC->FXOSCON ; AUX Clock Selector 5 setup m w 0xFFFB01C0 0x01000000 ; MC_CGM_AC5_SC ; Enable PLL for DRUN mode m w 0xFFFB802C 0x00000040 ; MC_ME_DRUN_MC->PLLON ; Set PLL0 to 160MHz (40MHz XTAL) ; VCO Frequency Range 600 - 1280 MHz ; RFDPHI1 = 10, RFDPHI = 4, PREDIV = 4, MFD = 0x40h (64) m w 0xFFFB00A8 0x50014040 ; PLLDIG_PLLDV m w 0xFFFB0098 0x09C3C000 ; PLLDIG_PLLCAL3 ; switch to PLL ; FLASH in normal mode, PLLON, FXOSC ON, Use PLL_PHI_0 m w 0xFFFB802C 0x00130172 ; MC_ME_DRUN_MC ; PLL_CLKOUT1 m w 0xFFFB08C0 0x02000000 ; MC_CGM_AC6_SC ; Mode transition to apply the PLL0 setup and set Normal mode with PLL running m w 0xFFFB8004 0x30005AF0 ; MC_ME_MCTL, DRUN Mode & Key m w 0xFFFB8004 0x3000A50F ; MC_ME_MCTL, DRUN Mode & Key wait 200 ; Configure PA[0] as SYSCLK0 ; SIUL must be configured after mode transition! m w 0xFFFC0240+0x19C 0x02000003 ; SIUL2_MSCR(103), PG[7] - ODC_PUSH_PULL and SSS_PF8_SYSCLK0 echo Please wait, initializing SRAM... ; mem write doesn't initialize the memory. ; "mem test" or "mem speed" should be used mem speed 0x40000000 0x40000/8 ; 256 KB, /4 for speed ;mem speed 0x50000000 0 0x4000/4 ; Core 0 I-MEM 16KB ;mem speed 0x50800000 0 0x8000/4 ; Core 0 D-MEM 32KB ;mem speed 0x51000000 0 0x4000/4 ; Core 1 I-MEM 16KB ;mem speed 0x51800000 0 0x8000/4 ; Core 1 D-MEM 32KB [FLASH_MPC5XXX] CHIP = MPC5xxx ; internal FLASH AGENT_MODE = VLE ; VLE or BOOKE: depends on the SRAM configuration FILE = "test32k.bin", BIN, 0x01000000 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 ; enable CLI over RS232 ;TCP_PORT = 2023 ; enable serial over TCP/IP [TELNET] PROMPT = "mpc5748g> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog