;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC8321 processor ; ; Ronetix GmbH ; ; Supported devices : MPC8321 ; ; Board : custom board ; ; Revision : 1.0 ; ; Date : October 24, 2008 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port GDB_READ_INGNORE_TIME = 3000 [TARGET] PLATFORM = MPC8300 ; platform is PowerPC [PLATFORM_MPC8300] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 1000, 16000 ; JTAG Clock in [kHz] - 10kHz jtag clock for init operations and 16MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 500 CORE0 = MPC8321 ; TAP is PowerPC CPU CORE0_INIT = INIT_MPC8321 CORE0_STARTUP_MODE = RESET CORE0_BOOT_ADDR = 0x00100 CORE0_RCW = 0xA2600000 0x420500A6 ;override reset configuration words CORE0_MMU_PTBASE = 0x000000F0 CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_UBOOT CORE0_WORKSPACE_ADDR = 0x00000000 ; start address of workspace for flash programmer CORE0_WORKSPACE_LEN = 0x10600 ; length of workspace in bytes ; Default path to be used if only a file name (without the full path) is ; provided to a PEEDI command or for the FILE parameter in the Flash sections ; Examples: ; In a console: ; "flash prog tftp://192.168.3.1/image.elf" ; is equal to ; "flash prog image.elf" ; ; In a Flash Profile: ; FILE="tftp://192.168.3.1/image.bin", BIN, 0 ; is equal to ; FILE="image.bin", BIN, 0 ; CORE0_PATH = "tftp://192.168.3.1" ;CORE0_PATH = "card://" CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file [INIT_MPC8321] ; Move MBAR to 0xE0000000 set MBAR 0xFF400000 mem write 0xFF400000 0xE0000000 ; MABR to 0xE0000000 set MBAR 0xE0000000 mem write 0xe0000204 0xffff0000 ; SWCRR: disable watchdog mem write 0xe0000110 0x00C00000 ; SPCR : enable timebase unit mem write 0xe00050d4 0x80000002 ; LCRR ; Initialize LAWBAR's mem write 0xE0000020 0xFE000000 ; LBLAWBAR0 : Flash mem write 0xe0000024 0x80000018 ; LBLAWAR0 mem write 0xe0000028 0x00000000 ; LBLAWBAR1 : BCSR mem write 0xe000002C 0x00000000 ; LBLAWAR1 mem write 0xe0000030 0x0F000000 ; LBLAWBAR2 : SDRAM mem write 0xe0000034 0x80000013 ; LBLAWAR2 mem write 0xe0000038 0xF8008000 ; LBLAWBAR3 mem write 0xe000003c 0x8000000F ; LBLAWAR3 mem write 0xe00000A0 0x00000000 ; DDRLAWBAR0 : DDR Main SODIMM mem write 0xe00000A4 0x80000019 ; DDRLAWAR0 mem write 0xe00000A8 0x00000000 ; DDRLAWBAR1 mem write 0xe00000AC 0x00000000 ; DDRLAWAR1 ; Setup DDR mem write 0xe0000128 0x73000002 ; DDRCDR mem write 0xe0002130 0x02000000 ; DDR_CLK_CNTL mem write 0xe0002000 0x00000003 ; CS0_BNDS mem write 0xe0002080 0x80840101 ; CS0_CONFIG mem write 0xe0002104 0x00220802 ; TIMING_CFG_0 mem write 0xe0002108 0x3935D322 ; TIMING_CFG_1 mem write 0xe000210C 0x0F9048CA ; TIMING_CFG_2 mem write 0xe0002100 0x00000000 ; TIMING_CFG_3 mem write 0xe0002110 0x43080000 ; DDR_CFG mem write 0xe0002114 0x00401000 ; DDR_CFG_2 mem write 0xe0002118 0x44400232 ; DDR_MODE mem write 0xe000211C 0x8000c000 ; DDR_MODE_2 mem write 0xe0002124 0x03200064 ; DDR_INTERVAL wait 100 mem write 0xe0002110 0xc3080000 ; DDR_CFG ; Setup chip selects mem write 0xe0005004 0xFE006FF7 ;OR0 : Flash mem write 0xe0005000 0xFE001001 ;BR0 : Flash mem write 0xe000500C 0x00000000 ;OR1 : BCSR mem write 0xe0005008 0x00000000 ;BR1 : BCSR set msr 0 ; let the interupt vectors point to valid RAM [FLASH_UBOOT] CHIP = S29GL128N ; flash chip ACCESS_METHOD = AGENT ; program method AGENT CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 1 ; one chip is used BASE_ADDR = 0xFF000000 ; chip is mapped at 0xFF000000 FILE = "myfile", BIN, 0xFF000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc8321> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program