;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC MPC8560 processor ; ; Ronetix GmbH ; ; Supported devices : MPC8560 ; ; Board : Wind River SBC8560 ; ; Revision : 1.0 ; ; Date : Sep 27, 2017 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8500 ; platform is MPC8500 [PLATFORM_MPC8500] JTAG_CHAIN = 8 JTAG_CLOCK = 20000 DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET WAKEUP_TIME = 2000 CORE0 = MPC8560 CORE0_INIT = INIT_MPC8560 CORE0_STARTUP_MODE = LOOP CORE0_BREAKMODE = soft CORE0_ENDIAN = big CORE0_FLASH0 = FLASH_NOR CORE0_WORKSPACE = 0x00000000, 0x10000 ; workspace for flash programmer CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.60" ; default path ;CORE0_MMU_TRANS = 0xC0000000 ; used when CORE0_INIT = INIT_BOOT ;CORE0_MMU_PTBASE = 0xF0 ; [INIT_MPC8560] ; init core register ; ; define maximal transfer size ;TSZ4 0x00000000 0xffffffff ; ; Move the L2SRAM to the initial MMU page mem write 0xFF720000 0x68010000 ;L2CTL mem write 0xFF720100 0xFFFC0000 ;L2SRBAR0 mem write 0xFF720000 0xA8010000 ;L2CTL ; ; Clear L2SRAM with DMA ;mem write 0xff721110 0x00040000 ;SATR0 SREADTTYPE=Read, don't snoop ;mem write 0xff721114 0xff700004 ;SAR0 Dummy source register ;mem write 0xff721118 0x00050000 ;DATR0 DWRITETTTYPE=Write, snoop local processor ;mem write 0xff721120 0x00040000 ;BCR0 Size ;mem write 0xff721100 0x0f009404 ;MR0 BWC=f,SAHTS=2(4 bytes),SAHE=1,SWSM=Dest,SRW=1,CTM=1,CS=0 ;mem write 0xff72111c 0xfffc0000 ;DAR0 which sets CS=1 ;wait 200 ;let DMA complete ;mem write 0xff721100 0x00000000 ;MR0 reset condition ; ; load and execute boot code (needed if STARTUP HALT) ;mem write 0xfffffffc 0x48000000 ;loop ;EXEC 0xfffffffc 1000 ; ; load TLB entries, helper code @ 0xfffff000 mem write 0xfffff000 0x7c0007a4 ;tlbwe mem write 0xfffff004 0x7c0004ac ;msync mem write 0xfffff008 0x48000000 ;loop ; ; 1MB TLB1 #1 CCSRBAR 0x40000000 - 0x400fffff set spr 624 0x10010000 ;MAS0: set spr 625 0x80000500 ;MAS1: set spr 626 0x40000008 ;MAS2: set spr 627 0x4000003f ;MAS3: set spr 628 0x00000000 ;MAS4: go 0xfffff000 halt ; ; 256MB MB TLB1 #2 DDR 0x0 - 0x0fffffff set spr 624 0x10020000 ;MAS0: set spr 625 0x80000900 ;MAS1: set spr 626 0x00000000 ;MAS2: set spr 627 0x0000003f ;MAS3: go 0xfffff000 halt ; ; 256MB MB TLB1 #3 DDR 0x10000000 - 0x1fffffff set spr 624 0x10030000 ;MAS0: set spr 625 0x80000900 ;MAS1: set spr 626 0x10000000 ;MAS2: set spr 627 0x1000003f ;MAS3: go 0xfffff000 halt ; ; 64 MB TLB1 #4 FLASH: 0xfc000000 - 0xfcffffff set spr 624 0x10040000 ;MAS0: set spr 625 0x80000800 ;MAS1: set spr 626 0xFC000008 ;MAS2: set spr 627 0xFC00003f ;MAS3: go 0xfffff000 halt ; ; 4KB TLB1 #5 - Local Bus FPGA Control Port - 0x30000000 - 0x30001000 set spr 624 0x10050000 ;MAS0: set spr 625 0x80000100 ;MAS1: set spr 626 0x30000008 ;MAS2: set spr 627 0x3000003f ;MAS3: go 0xfffff000 halt ; ; 4KB TLB1 #6 - Local Bus DMSC I/O - 0x31000000 - 0x31000fff set spr 624 0x10060000 ;MAS0: set spr 625 0x80000100 ;MAS1: set spr 626 0x31000008 ;MAS2: set spr 627 0x3000003f ;MAS3: go 0xfffff000 halt ; 4KB TLB1 #7 - Local Bus DMSC S/C - 0x32000000 - 0x320000fff set spr 624 0x10070000 ;MAS0: set spr 625 0x80000100 ;MAS1: set spr 626 0x32000008 ;MAS2: set spr 627 0x3200003f ;MAS3: go 0xfffff000 halt ; 256MB TLB1 #8 - Local Bus BBUS Master 1 of 2 - 0x60000000 - 0x60000003f set spr 624 0x10080000 ;MAS0: set spr 625 0x80000900 ;MAS1: set spr 626 0x60000008 ;MAS2: set spr 627 0x6000003f ;MAS3: go 0xfffff000 halt ; 256MB TLB1 #9 - Local Bus BBUS Master 2 of 2 - 0x70000000 - 0x7100003f set spr 624 0x10090000 ;MAS0: set spr 625 0x80000900 ;MAS1: set spr 626 0x70000008 ;MAS2: set spr 627 0x7000003f ;MAS3: go 0xfffff000 halt ; ; 4MB TLB1 #10 - Local Bus BBUS Slave DPRAM - 0xe0000000 - 0xe000003f set spr 624 0x100a0000 ;MAS0: set spr 625 0x80000600 ;MAS1: set spr 626 0xe0000008 ;MAS2: set spr 627 0xe000003f ;MAS3: go 0xfffff000 halt ; ; 4KB TLB1 #11 - Local Bus USB - 0x50000000 - 0x5000003f set spr 624 0x100b0000 ;MAS0: set spr 625 0x80000100 ;MAS1: set spr 626 0x50000008 ;MAS2: set spr 627 0x5000003f ;MAS3: go 0xfffff000 halt ; ; Remove the L2SRAM from the initial MMU page mem write 0xFF720000 0x28010000 ;L2CTL mem write 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0x40000000 mem write 0xff700000 0x00040000 ;CCSRBAR to 0x40000000 ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; configure local access windows ; ; Window 0: DDR = F : ; Window 1: Local Bus = 4 : FPGA Control : 4KB : 0x30000000 ; Window 2: Local Bus = 4 : DMSC I/O : 4KB : 0x31000000 ; Window 3: Local Bus = 4 : DMSC S/C : 4KB : 0x32000000 ; Window 4: Local Bus = 4 : USB : 4KB : 0x50000000 ; Window 5: Local Bus = 4 : BBUS Master : 512MB : 0x60000000 ; Window 6: Local Bus = 4 : BBUS Slave : 4MB : 0xe0000000 ; Window 7: Local Bus = 4 : Flash : 64MB : 0xfc000000 ; Initialize LAWBAR's ; LAWBAR0 ; bit 12 - 31 = 0x0 - base addr mem write 0x40000C08 0x00000000 ;LAWBAR0 : @0x00000000 ; LAWAR0 ; bit 1 = 1 - enable window ; bit 8-11 = F - DDR ; bit 26 - 31 = 512MB - size mem write 0x40000C10 0x80f0001C ;LAWAR0 : DDR/SDRAM 512M ; LAWBAR1 FPGA Base Address ; bit 12 - 31 = 0x30000000 - base addr mem write 0x40000C28 0x00030000 ;LAWBAR1 : @0x30000000 ; LAWAR1 FPGA Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 4KB - size mem write 0x40000C30 0x8040000b ;LAWAR1 : Local Bus 1GB ; LAWBAR2 DMSC I/O Base Address ; bit 12 - 31 = 0x31000000 - base addr mem write 0x40000c48 0x00031000 ; LAWAR2 DMSC I/O Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 4KB - size mem write 0x40000c50 0x8040000B ; LAWBAR3 DMSC S/C Base Address ; bit 12 - 31 = 0x32000000 - base addr mem write 0x40000c68 0x00032000 ; LAWAR3 DMSC S/C Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 4KB - size mem write 0x40000c70 0x8040000B ; LAWBAR4 USB Base Address ; bit 12 - 31 = 0x50000000 - base addr mem write 0x40000c88 0x00050000 ; LAWAR4 USB Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 4KB - size mem write 0x40000c90 0x8040000B ; LAWBAR5 BBUS Master Base Address ; bit 12 - 31 = 0x60000000 - base addr mem write 0x40000ca8 0x00060000 ; LAWAR5 BBUS Master Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 512MB - size mem write 0x40000cb0 0x8040001c ; LAWBAR6 BBUS Slave Base Address ; bit 12 - 31 = 0xe0000000 - base addr mem write 0x40000cc8 0x000e0000 ; LAWAR6 BBUS Slave Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 4MB - size mem write 0x40000cd0 0x80400015 ; LAWBAR7 Flash Base Address ; bit 12 - 31 = 0xfc000000 - base addr mem write 0x40000ce8 0x000fc000 ; LAWAR7 Flash Attributes ; bit 1 = 1 - enable window ; bit 8-11 = 4 - local bus ; bit 26 - 31 = 64MB - size mem write 0x40000cf0 0x80400019 ;################################################################### ; ; DDR initalization ; ; configure the appropriate DDR controller registers ; CS0_BNDS ; bit 8-15 - starting address, 512MB ; bit 24-31 - ending address mem write 0x40002000 0x0000001f ; DDR CS0 ; CS0_CONFIG ; bit 0 = 1 - CS_0_EN CS0 enable ; bit 8 = 0 - AP_0_EN auto precharge for w/r disable ; bit 21 - 23 = 2 - ROW_BITS_CS_0 14 rows ; bit 29 - 31 = 2 - COL_BITS_CS_0 10 columns mem write 0x40002080 0x80000202 ; TIMING_CONFIG_1 ; bit 1-3 = 3 - PRETOACT precharge activate interval 3 clock cycles ; bit 5-7 = 7 - ACTTOPRE activate to precharge interval 7 clock cycles ; bit 9-11 = 5 = ACTTORW activate to r/w interval 5 cloc cycles ; bit 13 - 15 = 4 - CASLAT CAS latency 4 clock cycles ; bit 16 - 19 = 4 - REFREC refresh recovery time 4 clock cycles ; bit 22 - 23 = 3 - WRREC data to precharge interval 3 clock cycles ; bit 25 - 27 = 2 - ACTTOACT activate to activate interval 2 clock cycles ; bit 30 - 31 = 1 - WRTORD write data to read command interval 1 clock cycle mem write 0x40002108 0x37544321 ; TIMING_CONFIG_2 ; bit 19-21 = b010 - WR_DATA_DELAY - 4/8 clock delay mem write 0x4000210C 0x00000800 ; disable the memory interface with DDR_SDRAM_CFG[MEM_EN] ; DDR_SDRAM_CFG ; bit 0 = 0 - MEM_EN SDRAM interface logic is disabled ; bit 1 = 0 - SREN disable self refresh during sleep ; bit 2 = 0 - ECC_EN disable ECC interrupt generation ; bit 3 = 0 - RD_EN unbuffered DIMMs ; bit 6 - 7 = 2 - SDRAM_TYPE DDR SDRAM ; bit 10 = 0 - DYN_PWR power management disabled mem write 0x40002110 0x02000000 ; DDR_SDRAM_MODE ; bit 0 - 15 = 0x0002, Reduced Drive Strength ; bit 16 - 31 = 0x0062 SDMODE mem write 0x40002118 0x00020062 ; DDR_SDRAM_INTERVAL ; bit 2 - 15 = 0x03a3 - REFINT ; bit 18 - 31 = 0 - BSTOPRE auto precharge r/w commands used mem write 0x40002124 0x03a30000 wait 200 ; enable the memory interface ; DDR_SDRAM_CFG ; bit 0 = 1 - MEM_EN SDRAM interface logic is disabled mem write 0x40002110 0xc2000000 ;################################################################################# ; configure local bus memory controller ; The CS0 configuration for GEC Flash ;mem write 0x40005000 0xFC001801 ; BR0 base address at 0xFC000000, port size 32 bit, GPCM, valid ;mem write 0x40005000 0xFC001001 ; BR0 base address at 0xFC000000, port size 16 bit, GPCM, valid mem write 0x40005000 0xFC000801 ; BR0 base address at 0xFC000000, port size 8 bit, GPCM, valid mem write 0x40005004 0xFC006FF7 ; OR0 32MB flash size, 15 w.s., timing relaxed ; The CS1 configuration for GEC FPGA Control Port mem write 0x40005008 0x30000801 ; BR1 base address at 0x30000000, port size 8 bit, GPCM, valid mem write 0x4000500c 0xFFFFEFF7 ; OR1 32KB size, 15 w.s., timing relaxed ; The GEC does not have BR2 / OR2 ; The CS3 configuration for GEC USB mem write 0x40005018 0x50000801 ; BR3 base address at 0x50000000, port size 8 bit, GPCM, valid mem write 0x4000501c 0xFFFFEFF7 ; OR3 32KB size, 15 w.s., timing relaxed ; The CS4 configuration for GEC BBus Dual Port RAM mem write 0x40005020 0xE0001801 ; BR4 base address at 0xE0000000, port size 32 bit, GPCM, valid mem write 0x40005024 0xFFC00810 ; OR4 4MB size, 1 w.s., normal timing ; The CS5 configuration for GEC DMSC I/O mem write 0x40005028 0x31001001 ; BR5 base address at 0x31000000, port size 16 bit, GPCM, valid mem write 0x4000502c 0xFFFFEFF7 ; OR5 32KB size, 15 w.s., timing relaxed ; The CS6 configuration for GEC BBus Master Gateway mem write 0x40005030 0x60001801 ; BR6 base address at 0x60000000, port size 32 bit, GPCM, valid mem write 0x40005034 0xE00000F8 ; OR6 512MB size, 15 w.s., timing relaxed ; The CS7 configuration for GEC DMSC S/C mem write 0x40005038 0x32001001 ; BR7 base address at 0x32000000, port size 16 bit, GPCM, valid mem write 0x4000503c 0xFFFFEFF7 ; OR7 32KB size, 15 w.s., timing relaxed ; Program Local BUS Controller Control Registers mem write 0x400050d0 0x00000000 ; LBCR 12-30 (configuration register) mem write 0x400050d4 0x00030008 ; LCRR 12-31, 3 external address delay cycles, 8 clock divisor ; ; Setup flash programming workspace in L2SRAM ;mem write 0x40020000 0x68010000 ;L2CTL ;mem write 0x40020100 0xf0000000 ;L2SRBAR0 ;mem write 0x40020000 0xA8010000 ;L2CTL ;set spr 63 0xf0000000 ;IVPR to workspace ;set spr 415 0x0001500 ;IVOR15 : Debug exception ;mem write 0xf0001500 0x48000000 ;write valid instruction ; ; Setup flash programming workspace in dual port RAM set spr 63 0x40080000 ;IVPR to workspace set spr 415 0x000007F0 ;IVOR15 : Debug exception mem write 0x400807F0 0x48000000 ;write valid instruction ; ; Setup for program execution mem write 0x40020000 0x28010000 ;L2CTL mem write 0x40020000 0x28000000 ;L2CTL set spr 63 0x00000000 ;IVPR to workspace set spr 406 0x0000700 ;IVOR6 : Program exception set spr 415 0x0001500 ;IVOR15 : Debug exception mem write 0x00000700 0x48000000 ;write valid instruction mem write 0x00001500 0x48000000 ;write valid instruction ; NOR Flash is 28F640J3 [FLASH_NOR] CHIP = CFI_FLASH ACCESS_METHOD = AGENT CHECK_ID = YES ; not used when CFI_FLASH CHIP_WIDTH = 8 CHIP_COUNT = 1 BASE_ADDR = 0xFC000000 FILE = "test512k.bin", BIN, 0xFC000000 AUTO_ERASE = NO AUTO_LOCK = NO [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "mpc8560> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program