;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for P1010 processor ; ; Ronetix GmbH ; ; Supported devices : Freescale P1010 ; ; Board : P1010RDB rev.A ; ; Revision : 1.0 ; ; Date : Dec 09, 2014 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8500 ; platform is MPC8500 [PLATFORM_MPC8500] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 10000 ; JTAG Clock in [kHz] - 8MHz jtag clock for init operations and for normal work DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = P1010 ; TAP is P1010 CPU CORE0_INIT = INIT_P1010 ; used to program code into FLASH CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_BOOT CORE0_FLASH1 = FLASH_BOOT CORE0_WORKSPACE = 0xF0002000, 0xE000 ; workspace for flash programmer CORE0_FILE = "ubrdb.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path ;CORE0_MMU_TRANS = 0xC0000000 ; used when CORE0_INIT = INIT_BOOT ;CORE0_MMU_PTBASE = 0 ; [INIT_P1010] ;mem wr 0xE0000000 0x0000FF70 ;CCSRBAR to 0xe0000000 ;================= setup TLB entries ========================= ; Move the L2SRAM to the initial MMU page mem wr 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error mem wr 0xFF720000 0x70010000 ;L2CTL mem wr 0xFF720100 0xFFFF0000 ;L2SRBAR0: map to 0x0_FFFF0000 mem wr 0xFF720104 0x00000000 ;L2SRBAREA0 mem wr 0xFF720000 0xB0010000 ;L2CTL: Entire array is a single SRAM ; Load TLB entries, helper code @ 0xfffff000 mem wr 0xfffffff4 0x7c0007a4 ;tlbwe mem wr 0xfffffff8 0x7c0004ac ;msync mem wr 0xfffffffc 0x48000000 ;loop set MAS4 0x00000000 set MAS6 0x00000000 go 0xfffffffc halt ; 256 MB TLB1 #0 0xf0000000 - 0xffffffff set MAS0 0x10000000 set MAS1 0x80000900 set MAS2 0xf0000008 set MAS3 0xf000003F go 0xfffffff4 halt ; 64 MB TLB1 #1 0xe0000000 - 0xe3ffffff set MAS0 0x10010000 set MAS1 0x80000800 set MAS2 0xe0000008 set MAS3 0xe000003F go 0xfffffff4 halt ; Remove the L2SRAM from the initial MMU page mem wr 0xFF720000 0x30010000 ;L2CTL mem wr 0xFF720000 0x30000000 ;L2CTL ;================= end setup TLB entries ===================== ;================= setup for flash programming =============== ; Move CCSRBAR from 0xFF700000 to 0xFFE00000 mem wr 0xff700000 0x000FFE00 ;CCSRBAR to 0xFFE00000 ; Initialize LAWBAR's mem wr 0xffe00C08 0x000EE000 ;LAWBAR0 : @0x00EE0000 mem wr 0xffe00C10 0x80400018 ;LAWAR0 : DDR/SDRAM 32MB mem wr 0xffe00C28 0x000FFB00 ;LAWBAR1 : @0xffb00000 mem wr 0xffe00C30 0x80400010 ;LAWAR1 : 128KB mem wr 0xffe00C48 0x000FF800 ;LAWBAR2 : @0xff800000 mem wr 0xffe00C50 0x80400013 ;LAWAR2 : NAND Flash 1MB mem write 0xffee0060 0xc0 ; PMUXCR1 ; Configure IFC controller for P1010RDB rev.A: Page = 512 bytes mem wr 0xffe1e0a0 0xffff0000 ; AM Bank Size mem wr 0xffe1e130 0x84800000 ; OR0 mem wr 0xffe1e1C0 0x020C0405 ; CS0 TIM0 mem wr 0xffe1e1c4 0x1D1D070C ; CS0 TIM1 mem wr 0xffe1e1c8 0x0180280F ; CS0 TIM2 mem wr 0xffe1e1cc 0x04000000 ; CS0 TIM3 mem wr 0xffe1e010 0xFF800083 ; CPSR Base address of CS0 (0xFF800000) ; Setup NAND chip select ; Configure IFC controller ; The latest PEEDI firmware setup automatically in OR0 the bits for ; page size, spare size, pages per block. The other bits are not modified ; and can be set in the configuration file. ;mem wr 0xffe1e0a0 0xffff0000 ; AM Bank Size ;mem wr 0xffe1e130 0x85082100 ; OR0 - page 2KB ;mem wr 0xffe1e130 0x85104100 ; OR0 - page 4KB ;mem wr 0xffe1e1C0 0x0E18070A ; CS0 TIM0 ;mem wr 0xffe1e1c4 0x32390E18 ; CS0 TIM1 ;mem wr 0xffe1e1c8 0x01E0501E ; CS0 TIM2 ;mem wr 0xffe1e1cc 0x00000000 ; CS0 TIM3 ;mem wr 0xffe1e010 0xFF800083 ; Base address of CS0 (0xFF800000) ; Setup flash programming workspace in L2SRAM mem wr 0xffe20e44 0x0000001c ;L2ERRDIS: disable parity error mem wr 0xffe20000 0x70010000 ;L2CTL mem wr 0xffe20100 0xF0000000 ;L2SRBAR0: map to 0xF0000000 mem wr 0xffe20104 0x00000000 ;L2SRBAREA0 mem wr 0xffe20000 0xB0010000 ;L2CTL set IVPR 0xf0000000 ;IVPR to workspace set IVOR0 0x00000000 ;IVOR15 : Debug exception set IVOR1 0x00000100 ;IVOR15 : Debug exception set IVOR2 0x00000200 ;IVOR15 : Debug exception set IVOR3 0x00000300 ;IVOR15 : Debug exception set IVOR4 0x00000400 ;IVOR15 : Debug exception set IVOR5 0x00000500 ;IVOR15 : Debug exception set IVOR6 0x00000600 ;IVOR15 : Debug exception set IVOR8 0x00000800 ;IVOR15 : Debug exception set IVOR10 0x00000A00 ;IVOR15 : Debug exception set IVOR11 0x00000B00 ;IVOR15 : Debug exception set IVOR12 0x00000C00 ;IVOR15 : Debug exception set IVOR13 0x00000D00 ;IVOR15 : Debug exception set IVOR14 0x00000E00 ;IVOR15 : Debug exception set IVOR15 0x00001500 ;IVOR15 : Debug exception mem wr 0xf0001500 0x48000000 ;write valid instruction mem wr 0xf0000000 0x7D821008 mem wr 0xf0000100 0x7D821008 mem wr 0xf0000200 0x7D821008 mem wr 0xf0000300 0x7D821008 mem wr 0xf0000400 0x7D821008 mem wr 0xf0000500 0x7D821008 mem wr 0xf0000600 0x7D821008 mem wr 0xf0000800 0x7D821008 mem wr 0xf0000A00 0x7D821008 mem wr 0xf0000B00 0x7D821008 mem wr 0xf0000C00 0x7D821008 mem wr 0xf0000D00 0x7D821008 mem wr 0xf0000E00 0x7D821008 [FLASH_BOOT] CHIP = NAND_FLASH CPU = P101X CMD_BASE = 0xFFE1E000 ; IFC address DATA_BASE = 0xFF800000 ; FCM address ADDR_BASE = 0 ; NAND chip select OOB_INFO = FF FILE = "test2m.bin", 0x0 ;AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "p1010> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ;AUTORUN = 3 ; user defined scripts 1 = erase 2 = prog 3 = do_all [erase] ; erase flash flash erase [prog] ; program flash flash query ; List the bad blocks flash info ; mark the bad blocks flash program card://ubrdb.bin 0x0 ; u-boot at 0x0 flash program card://dtb.bin 0x160000 ; dtb flash program uirdb.bin 0x200000 ; kernel flash program card://gz.bin 0x800000 ; compressed file system ; Marking bad blocks on 512 bytes NAND page devices ; need disabling the hardware ECC since it overwrites ; the bad block markers in page spare data [mark_bad_blocks] flash set 1 ; select NAND flash profile mem and 0xe0005008 0xFFFFF9FF ; disable hardware ECC flash info ; any flash command will mark the bad blocks mem or 0xe0005008 0x00000400 ; reenable hardware ECC [do_all] flash query ; List the bad blocks flash info ; mark the bad blocks flash erase flash program card://ubrdb.bin 0x0 flash program card://dtb.bin 0x160000 flash program uirdb.bin 0x200000 flash program card://gz.bin 0x800000 beep 500 100