;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for PowerPC P1011 processor ; ; Ronetix GmbH ; ; Supported devices : P1011 ; ; Board : Freescale P1020RDB ; ; Revision : 1.2 ; ; Date : June 9, 2011 ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = MPC8500 ; platform is MPC8500 [PLATFORM_MPC8500] JTAG_CHAIN = 8 ; list of IR length of all TAP controller in JTAG chain JTAG_CLOCK = 20000 ; JTAG Clock in [kHz] - 8MHz JTAG clock for init operations and for normal work DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = P1011 ; TAP is P1011 CPU CORE0_INIT = INIT_P1011 ; used to program code into FLASH CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = FLASH_NOR CORE0_FLASH1 = FLASH_NAND CORE0_WORKSPACE = 0x00000000, 0x10600 ; workspace for flash programmer CORE0_FILE = "myfile.bin", BIN, 0x2000000 ; default file CORE0_PATH = "tftp://192.168.3.1" ; default path ;CORE0_MMU_TRANS = 0xC0000000 ;CORE0_MMU_PTBASE = 0 [INIT_P1011] ;================= setup TLB entries =================== ; Move the 256kB L2SRAM to the initial MMU page mem write 0xFF720E44 0x0000001C ;L2ERRDIS: disable parity error mem write 0xFF720000 0x50010000 ;L2CTL mem write 0xFF720100 0xFFFC0000 ;L2SRBAR0: map to 0x0_FFFC0000 mem write 0xFF720104 0x00000000 ;L2SRBAREA0 mem write 0xFF720000 0x90010000 ;L2CTL ; ; load and execute some boot code mem write 0xfffffffc 0x48000000 ;loop go 0xfffffffc halt ; ; load TLB entries, helper code @ 0xfffff000 mem write 0xfffffff4 0x7c0007a4 ;tlbwe mem write 0xfffffff8 0x7c0004ac ;msync set MAS4 0x00000000 ;MAS4: set MAS6 0x00000000 ;MAS7: ; 64 MB TLB1 #0 0xfc000000 - 0xffffffff set MAS0 0x10000000 ;MAS0: set MAS1 0x80000800 ;MAS1: set MAS2 0xfc00000a ;MAS2: set MAS3 0xfc000015 ;MAS3: go 0xfffffff4 ha ; 1 GB TLB1 #1 0x80000000 - 0xbfffffff set MAS0 0x10010000 ;MAS0: set MAS1 0x80000a00 ;MAS1: set MAS2 0x8000000a ;MAS2: set MAS3 0x80000015 ;MAS3: go 0xfffffff4 ha ; 256 MB TLB1 #2 0xe0000000 - 0xefffffff set MAS0 0x10020000 ;MAS0: set MAS1 0x80000900 ;MAS1: set MAS2 0xe000000a ;MAS2: set MAS3 0xe0000015 ;MAS3: go 0xfffffff4 ha ; 256 MB TLB1 #3 0xc0000000 - 0xcfffffff set MAS0 0x10030000 ;MAS0: set MAS1 0x80000900 ;MAS1: set MAS2 0xc000000a ;MAS2: set MAS3 0xc0000015 ;MAS3: go 0xfffffff4 ha ; 256 MB TLB1 #4 0xd0000000 - 0xdfffffff set MAS0 0x10040000 ;MAS0: set MAS1 0x80000800 ;MAS1: set MAS2 0xd000000a ;MAS2: set MAS3 0xd0000015 ;MAS3: go 0xfffffff4 ha ; 1 GB TLB1 #5 0x00000000 - 0x3fffffff set MAS0 0x10050000 ;MAS0: set MAS1 0x80000a00 ;MAS1: set MAS2 0x00000000 ;MAS2: set MAS3 0x00000015 ;MAS3: go 0xfffffff4 ha ; Remove the L2SRAM from the initial MMU page mem write 0xFF720000 0x10010000 ;L2CTL mem write 0xFF720000 0x10000000 ;L2CTL ;================= end setup TLB entries ===================== ; ; ;================= setup memory controller =================== ; Let CCSRBAR at 0xff700000 ;mem write 0xff700000 0x000e0000 ;CCSRBAR to 0xe0000000 ; ; Initialize LAWBAR's mem write 0xff700C08 0x00000000 ;LAWBAR0 : @0x00000000 mem write 0xff700C10 0x80f0001e ;LAWAR0 : DDR/SDRAM 2GB mem write 0xff700C28 0x000c0000 ;LAWBAR1 : @0xc0000000 mem write 0xff700C30 0x8040001d ;LAWAR1 : Local Bus 1GB mem write 0xff700C48 0x00080000 ;LAWBAR2 : @0x80000000 mem write 0xff700C50 0x8000001d ;LAWAR2 : PCI 1GB ; Setup chip select mem write 0xff705004 0xff000ff7 ;OR0 : Flash mem write 0xff705000 0xef001001 ;BR0 : 16MB at 0xe8000000 mem write 0xff705008 0xFF000C21 ; BR1 base address at 0xF1000000, port size 8 bit, FCM, valid mem write 0xff70500C 0xFFF80396 ; OR1 32kB ; Setup DDR2 mem write 0xff702000 0x0000001f ;CS0_BNDS mem write 0xff702008 0x00000000 ;CS1_BNDS mem write 0xff702080 0x80014202 ;CS0_CONFIG mem write 0xff702084 0x00000000 ;CS1_CONFIG mem write 0xff7020C0 0x00000000 ;CS0_CONFIG_2 mem write 0xff7020C4 0x00000000 ;CS1_CONFIG_2 mem write 0xff702100 0x00030000 ;TIMING_CFG_3 mem write 0xff702104 0x55770802 ;TIMING_CFG_0 mem write 0xff702108 0x5f599543 ;TIMING_CFG_1 mem write 0xff70210C 0x0fa074d1 ;TIMING_CFG_2 mem write 0xff702110 0x43080000 ;DDR_CFG mem write 0xff702114 0x24401010 ;DDR_CFG_2 mem write 0xff702118 0x00040852 ;DDR_MODE mem write 0xff70211C 0x00000000 ;DDR_MODE_2 mem write 0xff702124 0x0a280100 ;DDR_INTERVAL mem write 0xff702128 0xdeadbeef ;DDR_DATA_INIT mem write 0xff702130 0x02800000 ;DDR_CLK_CNTL mem write 0xff702148 0x00000000 ;DDR_INIT_ADDR mem write 0xff70214C 0x00000000 ;DDR_INIT_EXT_ADDR mem write 0xff702160 0x00000000 ;TIMING_CFG_4 mem write 0xff702164 0x00000000 ;TIMING_CFG_5 mem write 0xff702170 0x00000000 ;DDR_ZQ_CNTL mem write 0xff702174 0x00000000 ;DDR_WRLVL_CNTL mem write 0xff702B28 0x00000000 ;DDRCDR_1 mem write 0xff702B2C 0x00000000 ;DDRCDR_2 wait 100 mem write 0xff702110 0xc3080000 ;DDR_CFG wait 1000 ; ;================= end setup memory controller =============== ; ; Setup debug vector for program execution set IVPR 0x00000000 ;IVPR : Exceptions at 0x00000000 set IVOR6 0x0000700 ;IVOR6 : Program exception set IVOR15 0x0001500 ;IVOR15 : Debug exception mem write 0x00000700 0x48000000 ;write valid instruction mem write 0x00001500 0x48000000 ;write valid instruction [FLASH_NOR] CHIP = CFI_FLASH ; flash chip ACCESS_METHOD = AGENT ; program method auto CHECK_ID = YES ; check chip ID BASE_ADDR = 0xEF000000 ; chip is mapped at 0xEF000000 FILE = "test.bin", BIN, 0xEF000000 ; file to program AUTO_ERASE = NO ; erase before program AUTO_LOCK = NO ; lock after program [FLASH_NAND] CHIP = NAND_FLASH CPU = MPC83XX CMD_BASE = 0xFF700000 ; CCSRBAR DATA_BASE = 0xFF000000 ; FCM address ADDR_BASE = 1 ; NAND chip select OOB_INFO = FF FILE = "test.bin", 0x0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "p1011> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program