;-------------------------------------------------------------------------- ; ; ; PEEDI target configuration file for Freescale T1040 processor ; ; Ronetix GmbH ; ; Supported devices : Freescale T1040 ; ; Board : T1040RDB ; Revision : 1.0 ; Date : February 9, 2016 ; ; The INIT section 'INIT_T1040' is used when programing NOR, NAND and SPI Flash. ; Without INIT section and CORE_RCW_* the board can be booted with: ; go 0xFFFFFFFC ; start from reset vector ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2020, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = QorIQ_P ; platform is QorIQ series [PLATFORM_QorIQ_P] JTAG_CHAIN = 8 ; list of IR lenght of all TAP controller in JTAG chain JTAG_CLOCK = 15000 ; JTAG Clock in [kHz] - 10MHz jtag clock for Linux kernel debugging DBGREQ_OUTPUT = HIGH TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; lenght of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 200 CORE0 = T1040A CORE0_INIT = INIT_T1040 ; used to program code into FLASH ;CORE0_INIT = INIT_LINUX CORE0_STARTUP_MODE = reset CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_ENDIAN = big ; core is little endian CORE0_FLASH0 = NOR_FLASH CORE0_FLASH1 = NOR_FLASH_DIRECT CORE0_FLASH2 = NAND_FLASH CORE0_FLASH3 = SPI_FLASH CORE0_WORKSPACE = 0x80000000, 0x4000 ; workspace for flash programmer CORE0_FILE = "myfile.bin", BIN, 0x80000000 ; default file CORE0_PATH = "tftp://192.168.3.60" ; default path CORE0_REGLIST = 32BIT ; use 64BIT if core is used in 64-bit mode CORE0_MEMACCESS = SAP; CORE ; use SAP for faster FLASH programming CORE0_RCW_SRC = 0x09A ; 0_1001_1110 : hard coded RCW. SYSCLK=66MHz, DDRCLK=100MHz CORE0_RCW6 = 0xFC027000 ; PBI_SRC disabled [] CORE1 = T1040B CORE1_INIT = INIT_MMU CORE1_STARTUP_MODE = reset CORE1_BREAKMODE = soft CORE1_ENDIAN = big CORE1_REGLIST = 32BIT CORE1_MEMACCESS = CORE CORE2 = T1040C CORE2_INIT = INIT_MMU CORE2_STARTUP_MODE = reset CORE2_BREAKMODE = soft CORE2_ENDIAN = big CORE2_REGLIST = 32BIT CORE2_MEMACCESS = CORE CORE3 = T1040D CORE3_INIT = INIT_MMU CORE3_STARTUP_MODE = reset CORE3_BREAKMODE = soft CORE3_ENDIAN = big CORE3_REGLIST = 32BIT CORE3_MEMACCESS = SAP [INIT_LINUX] break add hard 0xc08714ac go wait 30000 stop break del all beep 100 100 [INIT_T1040] ; Setup MMU ;1/0: ff000000->0_ff000000 16MB -I-G- RWXRWX set mas0 0x10000000 set mas1 0x80000700 set mas2 0xff00000a set mas3 0xff00003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX set mas0 0x10010000 set mas1 0x80000700 set mas2 0xfe00000a set mas3 0xfe00003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/2: e0000000->0_e0000000 256MB -I-G- RWXRWX set mas0 0x10020000 set mas1 0x80000900 set mas2 0xe000000a set mas3 0xe000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/3: 00000000->0_00000000 1GB ----- RWXRWX set mas0 0x10030000 set mas1 0x80000a00 set mas2 0x00000000 set mas3 0x0000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/4: 40000000->0_40000000 1GB ----- RWXRWX set mas0 0x10040000 set mas1 0x80000a00 set mas2 0x40000000 set mas3 0x4000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/5: 80000000->0_80000000 256kB ----- RWXRWX set mas0 0x10050000 set mas1 0x80000400 set mas2 0x80000000 set mas3 0x8000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ; Initialize LAWBAR's mem write 0xfe000c00 0x00000000 ;LAWBAR0 : Flash @0_e0000000 mem write 0xfe000c04 0xe0000000 mem write 0xfe000c08 0x81f0001b ;LAWAR0 : eLBC 256MB mem write 0xfe000c10 0x00000000 ;LAWBAR1 : CPC1/SRAM @0_80000000 mem write 0xfe000c14 0x80000000 mem write 0xfe000c18 0x81000011 ;LAWAR1 : DDR1/CPC1 1MB mem write 0xfe000df0 0x00000000 ;LAWBAR31: SDRAM @0_00000000 mem write 0xfe000df4 0x00000000 mem write 0xfe000df8 0x8100001e ;LAWAR31 : DDR1/CPC1 2GB ; Integrated Flash Controller (IFC) ; NOR chip select mem write 0xfe12400C 0x00000000 ;Map 128 MByte of NOR Flash to 0xe8000000 mem write 0xfe124010 0xe8000101 mem write 0xfe1240A0 0xf8000000 ; NAND chip select mem write 0xfe1240ac 0xffff0000 ; AM Bank Size mem write 0xfe12413c 0x85082100 ; OR0 mem write 0xfe1241f0 0x0E18070A ; CS0 TIM0 mem write 0xfe1241f4 0x32390E18 ; CS0 TIM1 mem write 0xfe1241f8 0x01E0501E ; CS0 TIM2 mem write 0xfe1241fc 0x00000000 ; CS0 TIM3 mem write 0xfe12401c 0xFF800083 ; Base address of CS1 (0xFF800000) ; Use L3 cache (CPC1) as SRAM at 0x80000000 mem write 0xfe010100 0x00000000 ;high address mem write 0xfe010104 0x80000007 ;all 8 ways as SRAM mem write 0xfe010000 0x80000000 ;CPC enable mem write 0xfe010F00 0x08000000 ;Speculation disable ; set default vector set ivpr 0x80000000 set pc 0x80000100 ; write DNH instruction to default vector mem write 0x80000000 0x4c00018c ;catch default vector ; write a loop to CPC1/SRAM (for test only) mem write 0x80000100 0x3c6005f6 ;lis r3,1526 (100'000'000) mem write 0x80000104 0x38800000 ;li r4,0 mem write 0x80000108 0x38a00000 ;li r5,0 mem write 0x8000010c 0x38a50008 ;addi r5,r5,8 mem write 0x80000110 0x38840008 ;addi r4,r4,8 mem write 0x80000114 0x3463ffff ;addic. r3,r3,-1 mem write 0x80000118 0x4082fff4 ;bne bc mem write 0x8000011c 0x4bffffe4 ;b b0 mem write 0x80000120 0x60000000 ;nop mem write 0x80000124 0x60000000 ;nop ; Release cores for booting mem write 0xfe0E00E4 0x0000000f ;BRR: release all cores [INIT_MMU] ; Setup MMU for core #1,#2,#3 ;1/1: fe000000->0_fe000000 16MB -I-G- RWXRWX set mas0 0x10010000 set mas1 0x80000700 set mas2 0xfe00000a set mas3 0xfe00003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C ;1/2: 80000000->0_80000000 256kB ----- RWXRWX set mas0 0x10020000 set mas1 0x80000400 set mas2 0x80000000 set mas3 0x8000003f set mas7 0x00000000 exec 0x4C00012C exec 0x7C0007A4 exec 0x4C00012C set ivpr 0x80000000 set pc 0x80000100 [NOR_FLASH] CHIP = CFI_FLASH CHIP_COUNT = 1 CHIP_WIDTH = 16 BASE_ADDR = 0xE8000000 ACCESS_METHOD = AGENT FILE = "test32k.bin", BIN, 0xe8a00000 [NOR_FLASH_DIRECT] CHIP = CFI_FLASH CHIP_COUNT = 1 CHIP_WIDTH = 16 BASE_ADDR = 0xE8000000 ACCESS_METHOD = DIRECT FILE = "test32k.bin", BIN, 0xe8a00000 [NAND_FLASH] CHIP = NAND_FLASH CPU = P101X CMD_BASE = 0xFE124000 ; IFC address DATA_BASE = 0xFF800000 ; FCM address ADDR_BASE = 1 ; NAND chip select OOB_INFO = FF FILE = "test.bin", 0x0 ;AUTO_ERASE = YES ERASE_BAD_BLOCKS = NO [SPI_FLASH] CHIP = SPI25_FLASH CPU = FSL_ESPI CCSRBAR = 0xFE000000 SPI_CS = 0 [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "T1040> " ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 100 ; zummer volume [ACTIONS] ; user defined scripts 1 = erase 2 = prog [erase] ; erase flash flash erase [prog] ; program flash flash program