;-------------------------------------------------------------------------- ; ; PEEDI target configuration file ; ; (C)2010 KOAN software engineering - < www.koansoftware.com > ; ; Supported devices : PXA270 ; Board : Intel Mainstone I (Rev. E) ; ; Revision : 0.1 ; Date : 15-12-2010 ; Modifications : ; ; The file is delivered "AS IS" without warranty or condition of any ; kind, either express, implied or statutory. This includes without ; limitation any warranty or condition with respect to merchantability or ; fitness for any particular purpose, or against the infringements of ; intellectual property rights of others. ; ; FLASH base addr = 0x0000_0000 ; SDRAM base addr = 0xA300_0000 ; ;-------------------------------------------------------------------------- ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE=eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 2000 ; TCP/IP port [TARGET] PLATFORM = XScale ; platform is XScale [PLATFORM_XSCALE] JTAG_CHAIN = 7 ; list of IR length of all TAP controller in JTAG chain JTAG_CLOCK = 1000, 20000 ; JTAG Clock in [kHz] 1MHz JTAG clock for init ; operations and 20MHz for normal work TRST_TYPE = PUSHPULL ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 500 CORE0 = XScale, 0 ; TAP is XSCALE CPU ; if RESET than no code is executed after reset ; if STOP then PEEDI lets the target execute code for 300 ms. ; if RUN then the target excutes code until stopped by the telnet "halt" command CORE0_STARTUP_MODE = RESET CORE0_BREAKMODE = soft ; breakpoint mode: CORE0_INIT = INIT_MAINSTONE ; init section for XMATE board CORE0_FLASH0 = FLASH_28F ; flash section parameters CORE0_ENDIAN = LITTLE ; core is little endian CORE0_WORKSPACE_ADDR = 0xA0001000 ; start address of workspace for ; flash programmer CORE0_WORKSPACE_LEN = 0x10000 ; length of workspace in bytes 1.5KB ; agent + 8KB data buffer (min. ; 2048(0x800) bytes) CORE0_DEBUG_HANDLER_ADDR= 0xFE000000 ; debug handler base address CORE0_VECTOR_CATCH_MASK = 0 ;0x10 ; catch data abort exceptions CORE0_VECTOR_UNDEF = AUTO CORE0_VECTOR_SWI = AUTO CORE0_VECTOR_PABORT = AUTO CORE0_VECTOR_DABORT = AUTO CORE0_VECTOR_RES = AUTO CORE0_VECTOR_IRQ = AUTO CORE0_VECTOR_FIQ = AUTO CORE0_RELOCATED_UNDEF = AUTO CORE0_RELOCATED_SWI = AUTO CORE0_RELOCATED_PABORT = AUTO CORE0_RELOCATED_DABORT = AUTO CORE0_RELOCATED_RES = AUTO CORE0_RELOCATED_IRQ = AUTO CORE0_RELOCATED_FIQ = AUTO CORE0_FILE = "myfile.bin", BIN, 0x00400000 ; default file CORE0_PATH = "tftp://192.168.0.5" ; default path [INIT_XSCALE] break add watch 0xffff001C w 32 ; set watchpoint on FIQ vector break add watch 0x0000001C w 32 go ; start target wait 30000 stop ; wait to break go ; start again with updated vectors [INIT_MAINSTONE] ;--------------------------------------- ; ; setup GPIO ; memory write 0x40E00018 0x00008004 ;CPSR0 memory write 0x40E0001C 0x00020080 ;GPSR1 memory write 0x40E00020 0x16C14000 ;GPSR2 memory write 0x40E00118 0x0003E000 ;GPSR3 memory write 0x40E00024 0x00000000 ;GPCR0 memory write 0x40E00028 0x00000380 ;GPCR1 memory write 0x40E0002C 0x00000000 ;GPCR2 memory write 0x40E00124 0x00000000 ;GPCR3 memory write 0x40E0000C 0xCFE3BDE4 ;GPDR0 memory write 0x40E00010 0x003FAB81 ;GPDR1 memory write 0x40E00014 0x1EC3FC00 ;GPDR2 memory write 0x40E0010C 0x018FFE8F ;GPDR3 memory write 0x40E00054 0x84400000 ;GAFR0_L memory write 0x40E00058 0xA5000510 ;GAFR0_H memory write 0x40E0005C 0x000A9558 ;GAFR1_L memory write 0x40E00060 0x0005A1AA ;GAFR1_H memory write 0x40E00064 0x60000000 ;GAFR2_L memory write 0x40E00068 0x00000802 ;GAFR2_H memory write 0x40F00004 0x00000030 ;PSSR ; ; setup memory controller ; ; setup Flash and Sram ; See page 73-74 of Dev Kit memory write 0x48000008 0x23F2B8F2 ;MSC0 memory read 0x48000008 memory write 0x4800000C 0x0000CCD1 ;MSC1 memory read 0x4800000C memory write 0x48000010 0x0000B884 ;MSC2 memory read 0x48000010 memory write 0x48000014 0x00000001 ;MECR memory write 0x48000028 0x00000000 ;MCMEM0 memory write 0x4800002C 0x00000000 ;MCMEM1 memory write 0x48000030 0x00000000 ;MCATT0 memory write 0x48000034 0x00000000 ;MCATT1 memory write 0x48000038 0x00000000 ;MCIO0 memory write 0x4800003C 0x00000000 ;MCIO1 ; ; setup SDRAM ; see page 71 dev kit memory write 0x48000004 0x2013A01E ;MDREFR memory write 0x48000000 0x00000AC9 ;MDCNFG (NON-MCP Version) wait 200 ; memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory write 0xA0000000 0xA0000000 ;access SDRAM memory read 0xA0000000 ;read SDRAM memory write 0x48000040 0x00000000 ;MDMRS ;Unlock Flash ;memory write 0x00000000 0x00600060 ;unlock block 0 ;memory write 0x00000000 0x00D000D0 ;memory write 0x00020000 0x00600060 ;unlock block 1 ;memory write 0x00020000 0x00D000D0 ;--------------------------------------- [FLASH_28F] ; ; Depending on SW7 position you can use the flash on the mainboard or the flash on the processor card ; Set SW7=NODOT to use the MainBoard Flash ; CHIP = 28F128K18C ; 28F256L18-B ; flash chip ACCESS_METHOD = DIRECT ; program method auto CHECK_ID = YES ; check chip ID CHIP_WIDTH = 16 ; chip is in 16 bit configuration CHIP_COUNT = 2 ; two chip are used BASE_ADDR = 0 ; chip is mapped at 0x0000000 FILE = "u-boot.bin", BIN, 0 ; file to program AUTO_ERASE = YES ; erase before program AUTO_LOCK = NO ; lock after program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 2023 [TELNET] PROMPT = "mainstone>" ; telnet prompt ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts 1 = erase [erase] ; erase flash for JFFS2 flash erase f p tftp://192.168.0.251/mainstone/u-boot.bin bin 0x0 f p tftp://192.168.0.251/tcm-pxa270/zImage bin 0x00040000 f p tftp://192.168.0.251/tcm-pxa270/x11-image-kaeilos.jffs2 bin 0x00240000